A 56-mW 23-mm 2 single-chip 180-nm CMOS GPS receiver with 27.2-mW 4.1-mm 2 radio

IEEE Journal of Solid-State Circuits

Volumn 41, Issue 3, 2006, Pages 540-550

  Gramegna, Giuseppe ^a,c   Mattos, Philip G ^b   Losi, Marco ^a,d   Das, Sabyasachi ^a   Franciotta, Massimo ^a   Bellantone, Nino G ^a   Vaiana, Michele ^a,e   Mandatá, Valentina ^a   Paparo, Mario ^a  

^a STMICROELECTRONICS   (Italy)

^b STMicroelectronics Ltd Bristol   (United Kingdom)

^c Power Amplifier Design Team   (Italy)

^d Automotive Group   (Italy)

^e PA IC Team   (Italy)

Author keywords

Gps receiver; Low power dissipation; System on chip (soc)

Indexed keywords

GPS RECEIVER; LOW POWER DISSIPATION; SYSTEM-ON-CHIP (SOC);

CMOS INTEGRATED CIRCUITS; ELECTRIC POWER UTILIZATION; GLOBAL POSITIONING SYSTEM; MICROPROCESSOR CHIPS; RADIO;

SIGNAL RECEIVERS;

EID: 33644646887     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2005.864136     Document Type: Article

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