FLYSIG: Dataflow oriented delay-insensitive processor for rapid prototyping of signal processing

Proceedings of the International Workshop on Rapid System Prototyping

Volumn , Issue , 1998, Pages 136-141

  Hardt, Wolfram ^a   Kleinjohann, Bernd ^a  

^a UNIVERSITY OF PADERBORN   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER AIDED LOGIC DESIGN; LOGIC CIRCUITS; RAPID PROTOTYPING;

DATAFLOW ORIENTED DELAY INSENSITIVE PROCESSORS; FIELD PROGRAMMABLE GATE ARRAYS (FPGA);

SIGNAL PROCESSING;

EID: 0031677518     PISSN: 10746005     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (30)