General models and a reduction design technique for FPGA switch box designs

IEEE Transactions on Computers

Volumn 52, Issue 1, 2003, Pages 21-30

  Fan, Hongbing ^a   Liu, Jiping ^b   Wu, Yu Liang ^c  

^a UNIVERSITY OF VICTORIA   (Canada)

^b UNIVERSITY OF LETHBRIDGE   (Canada)

^c CHINESE UNIVERSITY OF HONG KONG   (Hong Kong)

Author keywords

Detailed routing; FPGA; Global routing; Hyper universal; Optimum design; Reduction technique; Switch box

Indexed keywords

ALGORITHMS; COMPUTER SIMULATION; GRAPH THEORY; PROBLEM SOLVING; SWITCHING; THEOREM PROVING;

GLOBAL ROUTING;

FIELD PROGRAMMABLE GATE ARRAYS;

EID: 0037247315     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/TC.2003.1159751     Document Type: Article

References (17)

1. M.J. Alexander and G. Robins, "New Performance FPGA Routing Algorithms," Proc. Design Automation Conf., pp. 562-567, 1995.
2. V. Betz, J. Rose, and A. Morquardt, Architecure and CAD for Deep-Submicron FPGAs. Boston: Kluwer Academic, 1999.
3. J.A. Bondy and U.S.R. Murty, Graph Theory with Applications. London: Macmillan Press, 1976.
4. S. Brown, R.J. Francise, J. Rose, and Z.G. Vranesic, Field-Programmable Gate Arrays, Boston: Kluwer Academic, 1992.
5. S. Brown, J. Rose, and Z.G. Vranesic, "A Detailed Router for Field-Programmable Gate Arrays," IEEE Trans. Computer-Aided Design, vol. 11, pp. 620-628, May 1992.
6. Y.W. Chang, D.F. Wong, and C.K. Wong, "Universal Switch Modules for FPGA Design," ACM Trans. Design Automation of Electronic Systems, vol. 1, no. 1, pp. 80-101, Jan. 1996.
7. A. Corp, The Maximalist Handbook, 1990.
8. H. Fan, P. Haxell, and J. Liu, "The Global Routing-A Combinatorial Design Problem," submitted.
9. Y.S. Lee and C.H. Wu, "A Performance and Routability Driven Router for FPGAs Considering Path Delays," Proc. Design Automation Conf., pp. 557-561, 1995.
10. J.F. Pan, Y.L. Wu, G. Yan, and C.K. Wong, "On the Optimal Four-Way Switch Box Routing Structures of FPGA Greedy Routing Architectures," Integration, the VLSI J., vol. 25, pp. 137-159, 1998.
11. J. Rose and S. Brown, "Flexibility of Interconnection Structures for Field-Programmable Gate Arrays," IEEE J. Solid-State Circuits, vol. 26, no. 3, pp. 277-282, 1991.
12. M. Shyu, G.M. Wu, Y.D. Chang, and Y.W. Chang, "Generic Universal Switch Blocks," IEEE Trans. Computers, vol. 49, no. 4, pp. 348-359, Apr. 2000.
13. Y.L. Wu and D. Chang, "On NP-Completeness of 2-D FPGA Routing Architectures and a Novel Solution," Proc. Int'l Conf. Computer-Aided-Design, pp. 362-366, 1994.
14. Y.L. Wu and M. Marek-Sadowska, "Routing for Array Type FPGAs," IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 16, no. 5, pp. 506-518, May 1997.
15. Y.L. Wu, S. Tsukiyalna, M. Marek-Sadowska, "On Computational Complexity of a Detailed Routing Problem in Two-Dimensional FPGAs," Proc. Fourth Great Lakes Symp. VLSI, Mar. 1994.
16. Y.L. Wu, S. Tsukiyama, and M. Marek-Sadowska, "Graph Based Analysis of 2-D FPGA Routing," IEEE Trans. Computer-Aided Design, vol. 15, no. 1, pp. 33-44, 1996.
17. Xilinx, Inc., The Programmable Logic Data Book, 1994.