A new static differential CMOS logic with superior low power performance

Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems

Volumn 2, Issue , 2003, Pages 810-813

  Elrabaa, Muhammad E S ^a  

^a KING FAHD UNIVERSITY OF PETROLEUM AND MINERALS   (Saudi Arabia)

Author keywords

[No Author keywords available]

Indexed keywords

CIRCUIT DELAYS; CIRCUIT TOPOLOGY; CMOS LOGIC; DIFFERENTIAL LOGIC; ENERGY EFFICIENT; EQUAL DELAYS; INPUT CAPACITANCE; LOW POWER PERFORMANCE; M-TECHNOLOGIES; MINIMUM DELAY; POWER DISSIPATION; POWER SUPPLY; SPICE SIMULATIONS;

CAPACITANCE; DELAY CIRCUITS; DIFFERENTIAL AMPLIFIERS; ELECTRIC NETWORK TOPOLOGY; LOGIC CIRCUITS; ENERGY EFFICIENCY; INTEGRATED CIRCUIT DESIGN;

SPICE;

EID: 33144475897     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICECS.2003.1301910     Document Type: Conference Paper

References (5)

1. L. G. Heller, el. Al., "Cascode voltage switch logic: A differential cmos logic family," in Proc. IEEE Int. Solid-State CircuitsConf, 1984, pp. 16-17.
2. Y. K. Tan and Y. C. Lim, "Self-Timed precharge latch," in Proc. Int. Symp. Circuits and Systems., 1990, pp. 566-569.
3. P. Ng, P. T. Balsara, and D. Steiss, "Performance of CMOS Differential Circuits, ".IEEE J. of Solid-State Circuits, vol.31,no. 6,pp. 841-846, June 1996.
4. M. W. Allam and M. I. Elmasry, "Dynamic Current Mode Logic (DyCML): A new low-power high-performance logic style, ".IEEE J. of Solid-State Circuits, vol.36, no. 3, pp. 550-558, March 2001.
5. A.M. Fahim and M.I. Elmasry, "Low-power high-performance arithmetic ciicuits and architectures,".IEEE J. of solid-State Circuits, vol. 37, no. 1, pp. 90-94, January 2002.