Study on the effects of wafer thinning and dicing on chip strength

IEEE Transactions on Advanced Packaging

Volumn 29, Issue 1, 2006, Pages 149-157

  Chen, Shoulung ^a,b   Tsai, C Z ^c   Wu, Enboa ^a   Shih, I G ^a   Chen, Y N ^a  

^a NATIONAL TAIWAN UNIVERSITY   (Taiwan)

^b INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE   (Taiwan)

^c MACRONIX INTERNATIONAL CO LTD   (Taiwan)

Author keywords

Backside mechanical grinding; Chip strength; Dicing; Plasma etching; Polishing; Weak regions

Indexed keywords

CRACK INITIATION; GRINDING (MACHINING); PLASMA ETCHING; POLISHING; PROBABILITY DISTRIBUTIONS; STRENGTH OF MATERIALS;

BACKSIDE MECHANICAL GRINDING; CHIP STRENGTH; DICING; WEAK REGIONS;

CHIP SCALE PACKAGES;

EID: 32444441084     PISSN: 15213323     EISSN: None     Source Type: Journal    
DOI: 10.1109/TADVP.2005.849552     Document Type: Article

References (10)

1. L. Wu, J. Chan, and C. S. Hsiao, "Cost-performance wafer thinning technology," in Proc. IEEE Electronic Components Technology Conf., 2003, pp. 1463-1467.
2. I. Blech and D. Dang, "Silicon wafer deformation after backside grinding," Solid State Tech., vol. 37, no. 8, pp. 74-76, 1994.
3. S. Lee, S. Sim, Y. Chung, Y. Jang, and H. Cho, "Fracture strength measurement of silicon chips," Jpn. J. Appl. Phys., vol. 36, pp. 3374-3380, 1997.
4. K. McGuire, S. Danyluk, T. L. Baker, J. W. Rupnow, and D. McLaughlin, "The influence of backgrinding on the fracture strength of 100 mm diameter (1 1 1) p-type silicon wafer," J. Mater. Sci., vol. 32, pp. 1017-1024, 1997.
5. S. F. Popelar, "An investigation into the fracture of silicon die used in flip chip applications," in Proc. Int. Symp. Advanced Packaging Materials, Mar. 15-18, 1998, pp. 41-48.
6. B. H. Yeung, V. Hause, and T. Lee, "Assessment of backside process through die strength evaluation," IEEE Trans. Adv. Pack., vol. 23, no. 3, pp. 582-587, Aug. 2000.
7. ASTM Industrial Standard, E 855, 1983.
8. E. Gaulhofer and H. Oyrer, "Wafer thinning and strength enhancement to meet emerging packaging requirement," presented at the Semicon Europa, Munich, Germany, 2000.
9. E. Wu, I. G. Shih, Y. N. Chen, S. Chen, C. Z. Tsai, and C. A. Shao, "Influence of grinding process on semiconductor chip strength," in Proc. IEEE Electronic Components Technology Conf., 2002, pp. 1617-1621.
10. S. Chen, "Analysis of chip strength and optimal design of large-die flip chip packages," M.S. thesis, Institute of Applied Mechanics, National Taiwan University, Taiwan, R.O.C., 2001.