-
1
-
-
0024173160
-
From substrate to VLSI: Investigation of hardened SIMOX without epitaxy, for dose, dose rate and SEU phenomena
-
J.L. Leray, E. Dupont-Nivet, O. Musseau, Y.M. Coïc, A. Umbert, and P. Lalande From substrate to VLSI: investigation of hardened SIMOX without epitaxy, for dose, dose rate and SEU phenomena IEEE Trans Nucl Sci 35 6 1988 1355 1360
-
(1988)
IEEE Trans Nucl Sci
, vol.35
, Issue.6
, pp. 1355-1360
-
-
Leray, J.L.1
Dupont-Nivet, E.2
Musseau, O.3
Coïc, Y.M.4
Umbert, A.5
Lalande, P.6
-
2
-
-
0031166726
-
Total dose effects on a fully-depleted SOI NMOSFET and its lateral parasitic transistor
-
V. Ferlet-Cavrois, O. Musseau, J.L. Leray, J.L. Pelloie, and C. Raynaud Total dose effects on a fully-depleted SOI NMOSFET and its lateral parasitic transistor IEEE Trans Electron Dev 44 6 1997 965 971
-
(1997)
IEEE Trans Electron Dev
, vol.44
, Issue.6
, pp. 965-971
-
-
Ferlet-Cavrois, V.1
Musseau, O.2
Leray, J.L.3
Pelloie, J.L.4
Raynaud, C.5
-
3
-
-
0027574251
-
Effects of total-dose irradiation on gate-all-around (GAA) devices
-
J.P. Colinge, and A. Terao Effects of total-dose irradiation on gate-all-around (GAA) devices IEEE Trans Nucl Sci 40 2 1993 78 86
-
(1993)
IEEE Trans Nucl Sci
, vol.40
, Issue.2
, pp. 78-86
-
-
Colinge, J.P.1
Terao, A.2
-
4
-
-
31844449766
-
Total-dose radiation hardness of the SOI 4-gate transistor (G4-FET)
-
K. Akarvardar, S. Cristoloveanu, R.D. Schrimpf, B. Dufrene, P. Gentil, and B.J. Blalock Total-dose radiation hardness of the SOI 4-gate transistor (G4-FET) Electrochem Soc Proc 2005-03 2005 99 106
-
(2005)
Electrochem Soc Proc
, vol.2005
, Issue.3
, pp. 99-106
-
-
Akarvardar, K.1
Cristoloveanu, S.2
Schrimpf, R.D.3
Dufrene, B.4
Gentil, P.5
Blalock, B.J.6
-
5
-
-
0033329310
-
Sub 50-nm FinFET: PMOS
-
Huang X, Lee WC, Kuo C, Hisamoto D, Chang L, Kedzierski J, et al., Sub 50-nm FinFET: PMOS. Technical digest of IEDM 199:67-70.
-
Technical Digest of IEDM
, vol.199
, pp. 67-70
-
-
Huang, X.1
Lee, W.C.2
Kuo, C.3
Hisamoto, D.4
Chang, L.5
Kedzierski, J.6
-
6
-
-
3943110263
-
A functional 41-stage ring oscillator using scaled FinFET devices with 25-nm gate lengths and 10-nm fin widths applicable for the 45-nm CMOS node
-
N. Collaert, A. Dixit, M. Goodwin, K.G. Anil, R. Rooyackers, and B. Degroote A functional 41-stage ring oscillator using scaled FinFET devices with 25-nm gate lengths and 10-nm fin widths applicable for the 45-nm CMOS node IEEE Electron Dev Lett 25 8 2004 568 570
-
(2004)
IEEE Electron Dev Lett
, vol.25
, Issue.8
, pp. 568-570
-
-
Collaert, N.1
Dixit, A.2
Goodwin, M.3
Anil, K.G.4
Rooyackers, R.5
Degroote, B.6
-
7
-
-
0023422261
-
Modeling of transconductance degradation and threshold voltage in thin oxide MOSFETs
-
H.S. Wong, M.H. White, T.J. Krutsck, and R.V. Booth Modeling of transconductance degradation and threshold voltage in thin oxide MOSFETs Solid-State Electron 30 9 1987 953 968
-
(1987)
Solid-State Electron
, vol.30
, Issue.9
, pp. 953-968
-
-
Wong, H.S.1
White, M.H.2
Krutsck, T.J.3
Booth, R.V.4
-
8
-
-
0028427763
-
Modeling of ultrathin double-gate nMOS/SOI transistors
-
P. Francis, A. Terao, D. Flandre, and F. Van de Wiele Modeling of ultrathin double-gate nMOS/SOI transistors Solid-State Electron 41 5 1994 715 720
-
(1994)
Solid-State Electron
, vol.41
, Issue.5
, pp. 715-720
-
-
Francis, P.1
Terao, A.2
Flandre, D.3
Van De Wiele, F.4
-
9
-
-
0042888776
-
Threshold voltage and subthreshold slope of multiple-gate SOI MOSFETs
-
J.P. Colinge, J.W. Park, and W. Xiong Threshold voltage and subthreshold slope of multiple-gate SOI MOSFETs IEEE Electron Dev Lett 24 8 2003 515 517
-
(2003)
IEEE Electron Dev Lett
, vol.24
, Issue.8
, pp. 515-517
-
-
Colinge, J.P.1
Park, J.W.2
Xiong, W.3
|