Impact of drain induced barrier lowering on read scheme in silicon nanocrystal memory with two-bit-per-cell operation

Japanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers

Volumn 45, Issue 2 A, 2006, Pages 638-642

  Park, Sangsu ^a,b   Im, Hyunsik ^b   Kim, Ilgweon ^a   Hiramoto, Toshiro ^a  

^a INSTITUTE OF INDUSTRIAL SCIENCE   (Japan)

^b Dongguk University   (South Korea)

Author keywords

Drain induced barrier lowering (DIBL); Low voltage and low power devices; Silicon nanocrystal; Threshold voltage

Indexed keywords

COMPUTER SIMULATION; NANOTECHNOLOGY; SILICON;

LOW-VOLTAGE AND LOW-POWER DEVICES; SILICON NANOCRYSTALS;

THRESHOLD VOLTAGE;

EID: 32244432415     PISSN: 00214922     EISSN: None     Source Type: Journal    
DOI: 10.1143/JJAP.45.638     Document Type: Review

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