A dictionary construction technique for code compression systems with echo instructions

Proceedings of the ACM SIGPLAN Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES)

Volumn , Issue , 2005, Pages 105-114

  Brisk, Philip ^a   Macbeth, Jamie ^a   Nahapetian, Ani ^a   Sarrafzadeh, Majid ^a  

^a Engineering IV   (United States)

Author keywords

(Dictionary) Compression; Echo Instructions; Scheduling

Indexed keywords

COMPUTER PROGRAMMING; DATA FLOW ANALYSIS; GRAPH THEORY; PROBLEM SOLVING; REDUNDANCY; SCHEDULING;

(DICTIONARY) COMPRESSION; ECHO INSTRUCTIONS; REDUNDANT SEQUENCES;

CODES (SYMBOLS);

EID: 31844452797     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1065910.1065926     Document Type: Conference Paper

References (25)

1. Advanced RISC Machines Ltd. An Introduction to Thumb, Ver. 2.0. White Paper, March 1995.
2. Benini, L., Macii, A., and Nannarelli, A. Cache-Code Compression for Energy Minimization in Embedded Processors. Int. Symp. Low Power Electronics and Design (ISLPED), 2001, 322-327.
3. Brisk, P., Nahapetian, A., and Sarrafzadeh, M. Instruction Selection for Compilers that Target Architectures with Echo Instructions. Int. Workshop on Software and Compilers for Embedded Systems (SCOPES), 2004, 229-243.
4. Chen, I., Bird, P., and Mudge, T. The Impact of Instruction Compression on I-cache Performance. Tech. Rpt. CSE-TR-330-97, EECS Dept., University of Michigan, 1997.
5. Chen, W-K., Li, B., and Gupta, R. Code Compaction of Matching Single-Entry Multiple-Exit Regions. Static Analysis Symp., 2003, 401-417.
6. Cooper, K. D., and McIntosh, N. Enhanced Code Compression for Embedded RISC Processors, Int. Conf. Programming Language Design and Implementation (PLDI), 1999, 139-149.
7. Corliss, M. L., Lewis, E. C., and Roth, A. A DISE Implementation of Dynamic Code Decompression. Conf. Languages, Compilers, and Tools for Embedded Systems (LCTES), 2003, 232-243.
8. De Sutter, B., De Bus, B., and De Bosschere, K. Sifting out the Mud:Low Level C++ Code Reuse. ACM SIGPLAN Conf. on Object-Oriented Programming, Systems, Languages, and Applications (OOPSLA), 2002, 275-291.
9. Debray, S., Evans, W., Muth, R., and de Sutter, B. Compiler Techniques for Code Compaction. ACM Trans. Programming Languages and Systems (TOPLAS), 22(2):347-415, 2000.
10. Fraser, C.W. An Inslruction for Direct Interprelation of LZ77-compressed Programs. MSR-TR-2002-90, Microsoft Research, September, 2002.
11. Fraser, C. W., Myers, E., and Wendt, A. Analyzing and Compressing Assembly Code. Int. Symp. Compiler Construction, 1984, 117-121.
12. Garey, M. R., and Johnson, D. S. Computers and Intractability: A guide to the Theory of NP-Completeness, New York, W. H. Freeman and Co., 1979.
13. Kastner R., Memik, S. O., Bozorgzadeh, E., and Sarrafzadeh, M. Instruction Generation for Hybrid-Reconfigurable Systems. ACM Trans. Design Automation of Embedded Systems (TODAES), 7(4):605-627, October, 2002.
14. Kemp, T. M., Montoye, R. K., Harper, J. D., Palmer, J. D., and Auerbach, D. J. A decompression core for PowerPC. IBM Journ. Research and Development, 42(6):807-812, November, 1998.
15. Kissel, K. D. MIPS16: High-density MIPS for the Embedded Market. White Paper. Silicon Graphics MIPS Group, 1997.
16. Kunchithapadam, K., and Larus, J. R. Using Lightweight Procedures to Improve Instruction Cache Performance. Tech. Rept. 1390, CS Dept., University of Wisconsin-Madison, 1999.
17. Lau, J., Schoenmakers, S., Sherwood, T., and Calder, B. Reducing Code Size with Echo Instructions. Int. Conf. Compilers, Architectures, and Synthesis for Embedded Systems (CASES), 2003, 84-94.
18. Lee, C., Potkonjak, M., Mangione-Smith, W. H. MediaBench: A Tool for Evaluating and Synthesizing Multimedia and Communications Systems. Int. Symp. Microarchitecture (MICRO-30), 1997, 330-335.
19. Lefurgy, C. R. Efficient Execution of Compressed Programs. Ph.D. Thesis, EECS Dept., University of Michigan, 2000.
20. Lekatsas, H., and Wolf, W. Code Compression for Embedded Systems. Design Automation Conf. (DAC), 1998, p. 516-521.
21. Liao, S., Devadas, S., and Keutzer, K. A Text-Compression-Based Method for Code Size Minimization in Embedded Systesms. ACM Trans. Design Automation of Electronic Systems (TODAES), 4(1): 12-38, January, 1999.
22. Runeson, J. Code Compression through Procedural Abstraction before Register Allocation. Master's Thesis. Computing Science Department, Uppsalla University, Sweden, March, 2000.
23. Storer, J. NP-Completeness Results Concerning Data Compression. Tech. Rpt. 234, Dept. Electrical Engineering and Computer Science, Princeton University, 1977.
24. Wolfe, A., and Chanin, A. Executing Compressed Programs on an Embedded RISC Architecture. Int. Symp. Microarchitecture (MICRO-25), 1992, 81-91.
25. http://www.eecs.harvard.edu/hube/research/machsuif.html