A DISE implementation of dynamic code decompression

Proceedings of the ACM SIGPLAN Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES)

Volumn , Issue , 2003, Pages 232-243

  Corliss, Marc L ^a   Lewis, E Christopher ^a   Roth, Amir ^a  

^a UNIVERSITY OF PENNSYLVANIA   (United States)

Author keywords

Code compression; Code decompression; DISE

Indexed keywords

DATA STORAGE EQUIPMENT; EMBEDDED SYSTEMS; MICROPROCESSOR CHIPS; PROGRAM PROCESSORS; STORAGE ALLOCATION (COMPUTER);

CODE COMPRESSION; CODE DECOMPRESSION; DYNAMIC INSTRUCTION STREAM EDITING;

COMPUTER SYSTEMS PROGRAMMING;

EID: 0242443857     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/780732.780765     Document Type: Conference Paper

References (23)

1. Advanced RISC Machines Ltd. An Introduction to Thumb, Mar. 1995.
2. D. Albonesi. Selective cache ways: On demand cache resource allocation. In Proc. 32nd International Symposium on Microarchitecture, pages 248-259, Nov. 1999.
3. G. Araujo, P. Centoducatte, and M. Cortes. Code compression based on operand factorization. In Proc. 31st International Symposium on Microarchitecture, pages 194-201, Dec. 1998.
4. D. Brooks, V. Tiwari, and M. Martonosi. Wattch: A framework for architectural-level power analysis and optimizations. In Proc. 27th International Symposium on Computer Architecture, pages 83-94, Jun. 2000.
5. D. Burger and T. M. Austin. The SimpleScalar tool set, version 2.0. Technical Report 1342, University of Wisconsin-Madison Computer Sciences Depatment, 1997.
6. K. Cooper and N. McIntosh. Enhanced code compression for embedded RISC processors. In Proc. of the ACM SIGPLAN '99 Conference on Programming Language Design and Implementation, pages 139-149, 1999.
7. M. L. Corliss, E. C. Lewis, and A. Roth, DISE: A programmable macro engine for customizing applications. In Proc. 30th International Symposium on Computer Architecture, Jun. 2003.
8. S. K. Debray, W. Evans, R. Muth, and J. D. Sutter. Compiler techniques for code compression. ACM Transactions on Programming Languages and Operating Systems, 22(2):378-415, Mar. 2000.
9. K. Diefendorf. K7 challenges Intel. Microprocessor Report, 12(14), Nov. 1998.
10. P. Glaskowsky. Pentium 4 (partially) previewed. Microprocessor Report, 14(8), Aug. 2000.
11. L. Gwenapp. P6 microcode can be patched. Microprocessor Report, 11(12) Sept. 1997.
12. T. M. Kemp, R. K. Montoye, D. J. Auerback, J. D. Harper, and J. D. Palmer. A decompression core for PowerPC. IBM Systems Journal, 42(6):807-812, Nov. 1998.
13. D. Kirovski, J. Kin, and W. Mangione-Smith. Procedure based program compression. In Proc. 30th International Symposium on Microarchitecture, pages 204-213, Dec. 1997.
14. K. Kissell. MIPS16: High-Density MIPS for the Embedded Market. Silicon Graphics MIPS Group, 1997.
15. C. Lee, M. Potkonjak, and W. Mangione-Smith. Mediabench: A tool for evaluating and synthesizing multimedia and communications systems. In Proc. 30th International Symposium on Microarchitecture, pages 330-335, Dec. 1997.
16. C. Lefurgy, P. Bird, I.-C. Cheng, and T. Mudge. Improving code density using compression techniques. In Proc. 30th International Symposium on Microarchitecture, pages 194-203, Dec. 1997.
17. C. Lefurgy, E. Piccininni, and T. Mudge. Reducing code size with run-time decompression. In Proc. 6th International Symposium on High-Performance Computer Architecture, pages 218-227, Jan. 2000.
18. H. Lekatsas, J. Henkel, and W. Wolf. Code compression for low power embedded system design. In Proc. 36th Design Automation Conference, pages 294-299, Jun. 2000.
19. S. Liao, S. Devadas, and K. Keutzer. A text-compression-based method for code size minimization in embedded systems. ACM Transactions on Design Automation of Electrical Systems, 4(1):12-38, Jan. 1999.
20. T. Szymanski. Assembling code for machines with span dependent instructions. Communications of the ACM, 21(4):300-308, Apr. 1978.
21. S. Wilton and N. Jouppi. An enhanced access and cycle time model for on-chip caches. Technical report, DEC Western Research Laboratory, 1994.
22. A. Wolfe and A. Chanin. Executing compressed programs on an embedded RISC architecture. In Proc. 25th International Symposium on Microarchitecture, pages 81-91, Dec. 1992.
23. S.-H. Yang, M. Powell, B. Falsafi, and T. Vijaykumar. Exploiting choice in resizable cache design to optimize deep-submicron processor energy-delay. In Proc. 8th International Symposium on High Performance Computer Architecture, Jan. 2002.