Multiple-symbol parallel decoding for variable length codes

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 12, Issue 7, 2004, Pages 676-685

  Nikara, Jari ^a,b   Vassiliadis, Stamatis ^b   Takala, Jarmo ^a   Liuha, Petri ^c  

^a TAMPERE UNIVERSITY OF TECHNOLOGY   (Finland)

^b DELFT UNIVERSITY OF TECHNOLOGY   (Netherlands)

^c NOKIA RESEARCH CENTER   (United States)

Author keywords

Critical path; Design; Gate array; Image processing; Reconfigurable systems; Video processing

Indexed keywords

COMPUTER HARDWARE; DATA FLOW ANALYSIS; DATA PROCESSING; FIELD PROGRAMMABLE GATE ARRAYS; IMAGE PROCESSING; PARAMETER ESTIMATION;

CRITICAL PATH; RECONFIGURABLE SYSTEMS; VARIABLE LENGTH DECODING (VLD); VIDEO PROCESSING;

DECODING;

EID: 3142731988     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2004.825840     Document Type: Conference Paper

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