Parallel multiple-symbol variable-length decoding

Proceedings-IEEE International Conference on Computer Design: VLSI in Computers and Processors

Volumn , Issue , 2002, Pages 126-131

  Nikara, Jari ^a   Vassiliadis, Stamatis ^b   Takala, Jarmo ^a   Sima, Mihai ^b   Liuha, Petri ^c  

^a TAMPERE UNIVERSITY OF TECHNOLOGY   (Finland)

^b DELFT UNIVERSITY OF TECHNOLOGY   (Netherlands)

^c NOKIA RESEARCH CENTER   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BUFFER CIRCUITS; COMPUTER HARDWARE DESCRIPTION LANGUAGES; FIELD PROGRAMMABLE GATE ARRAYS; IMAGE COMPRESSION; LOGIC DESIGN; TABLE LOOKUP;

MOVING PICTURES EXPERTS GROUP-2; VARIABLE-LENGTH DECODING; VERILOG HARDWARE DESCRIPTION LANGUAGES;

DECODING;

EID: 0036397184     PISSN: 10636404     EISSN: None     Source Type: Journal    
DOI: 10.1109/ICCD.2002.1106759     Document Type: Article

References (13)

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