A single-electron-transistor logic gate family and its application - Part I: Basic components for binary, multiple-valued and mixed-mode logic

Proceedings of The International Symposium on Multiple-Valued Logic

Volumn , Issue , 2004, Pages 262-268

  Degawa, Katsuhiko ^a   Aoki, Takafumi ^a   Higuchi, Tatsuo ^b   Inokawa, Hiroshi ^c   Takahashi, Yasuo ^c  

^a TOHOKU UNIVERSITY   (Japan)

^b TOHOKU INSTITUTE OF TECHNOLOGY   (Japan)

^c NTT Basic Research Laboratories   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; FORMAL LOGIC; FUNCTIONS; IMAGE SENSORS; MATHEMATICAL MODELS; TRANSISTORS;

FUNCTIONAL DENSITY; POWER OPERATIONS; SINGLE ELECTRON TRANSISTORS (SET);

LOGIC GATES;

EID: 3142704548     PISSN: 0195623X     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (8)

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