A single-electron-transistor logic gate family and its application - Part II: Design and simulation of a 7-3 parallel counter with linear summation and multiple-valued latch functions

Proceedings of The International Symposium on Multiple-Valued Logic

Volumn , Issue , 2004, Pages 269-274

  Inokawa, Hiroshi ^a   Takahashi, Yasuo ^a   Degawa, Katsuhiko ^b   Aoki, Takafumi ^b   Higuchi, Tatsuo ^c  

^a NTT Basic Research Laboratories   (Japan)

^b TOHOKU UNIVERSITY   (Japan)

^c TOHOKU INSTITUTE OF TECHNOLOGY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; ELECTRON TRANSITIONS; FUNCTIONS; INTEGRATED CIRCUITS; PRODUCT DESIGN; TRANSISTORS; VOLTAGE DIVIDERS;

LINEAR SUMMATION; POWER CONSUMPTION; SINGLE ELECTRON TRANSISTORS (SET);

LOGIC GATES;

EID: 3142720637     PISSN: 0195623X     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

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