Multiple-valued logic-in-memory VLSI architecture based on floating-gate-MOS pass-transistor logic

IEICE Transactions on Electronics

Volumn E82-C, Issue 9, 1999, Pages 1662-1668

  Hanyu, Takahiro ^a   Kameyama, Michitaka ^a  

^a TOHOKU UNIVERSITY   (Japan)

Author keywords

Flash EEP ROM technology; Floating gate MOS transistor; Four valued full adder; Logic in memory structure; Manhattan distance; Pass transistor network

Indexed keywords

CMOS INTEGRATED CIRCUITS; DATA STORAGE EQUIPMENT; LOGIC GATES; MOSFET DEVICES; PATTERN RECOGNITION; PROM; THRESHOLD VOLTAGE; VLSI CIRCUITS;

ELECTRONICALLY ERASABLE PROGRAMMABLE READ ONLY MEMORY; FLOATING GATE MOS TRANSISTOR; FOUR VALUED FULL ADDER; LOGIC IN MEMORY STRUCTURE; MANHATTAN DISTANCE; PASS TRANSISTOR NETWORKS;

MANY VALUED LOGICS;

EID: 0033322562     PISSN: 09168524     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article

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