Bias temperature instability assessment of n- and p-channel MOS transistors using a polysilicon resistive heated scribe lane test structure

Microelectronics Reliability

Volumn 44, Issue 8, 2004, Pages 1251-1262

  Muth, Werner ^a   Walter, Wolfgang ^a  

^a INFINEON TECHNOLOGIES AG   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; CMOS INTEGRATED CIRCUITS; EMBEDDED SYSTEMS; MOS DEVICES; MOSFET DEVICES; POLYSILICON; SEMICONDUCTOR JUNCTIONS; THERMAL STRESS;

BIAS TEMPERATURE INSTABILITY (BTI); POLYSILICON HEATERS; WAFER LEVEL DEVICES; WAFER LEVEL RELIABILITY (WLR);

MICROELECTRONICS;

EID: 3142699325     PISSN: 00262714     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.microrel.2004.04.011     Document Type: Article

References (14)

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