Field programmable gate array (FPGA) for iterative code evaluation

IEEE Transactions on Magnetics

Volumn 42, Issue 2, 2006, Pages 226-231

  Sun, Lingyan ^a   Song, Hongwei ^b   Keirn, Zak ^b   Kumar, B V K V ^a  

^a CARNEGIE MELLON UNIVERSITY   (United States)

^b Agere Systems   (United States)

Author keywords

Error statistics; FPGA; Iterative decoding; LDPC; TPC

Indexed keywords

DIGITAL STORAGE; ENCODING (SYMBOLS); ERROR ANALYSIS; FIELD PROGRAMMABLE GATE ARRAYS; ITERATIVE METHODS; MAGNETIC RECORDING; TURBO CODES;

ITERATIVE DECODING; PARTIAL RESPONSE (PR) CHANNEL; REED-SOLOMON (RS) CODE; TPC;

DATA STORAGE EQUIPMENT;

EID: 31344456726     PISSN: 00189464     EISSN: None     Source Type: Journal    
DOI: 10.1109/TMAG.2005.861744     Document Type: Article

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