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Volumn 54, Issue 1, 2006, Pages 13-17

An innovative low-density parity-check code design with near-Shannon-limit performance and simple implementation

Author keywords

Digital video broadcasting (DVB); High order modulation; Iterative decoding; Low density parity check (LDPC) codes; Very large scale integration (VLSI) implementation

Indexed keywords

AMPLITUDE MODULATION; CODES (SYMBOLS); DECODING; MATRIX ALGEBRA; PHASE SHIFT KEYING;

EID: 31344438070     PISSN: 00906778     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCOMM.2005.861681     Document Type: Article
Times cited : (39)

References (13)
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  • 2
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    • D. J. MacKay and R. M. Neal, "Near-Shannon-limit performance of low-density parity-check codes," Electron. Lett., vol. 33, no. 6, pp. 457-458, Mar. 1997.
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  • 3
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    • Richardson, T.1    Shokrollahi, A.2    Urbanke, R.3
  • 4
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    • Al-Rawi, G.1    Cioffi, J.2
  • 5
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    • Monterey, CA
    • M. Mansour and S. Shanbhag, "Low power VLSI decoder architectures for LDPC codes," in Proc. ISLPED, Monterey, CA, 2002, pp. 284-289.
    • (2002) Proc. ISLPED , pp. 284-289
    • Mansour, M.1    Shanbhag, S.2
  • 6
    • 31344445796 scopus 로고    scopus 로고
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    • W. Lee and A. Wu, "VLSI implementation for LDPC decoder," in Proc. ICECS, 2001, pp. 1223-1226.
    • (2001) Proc. ICECS , pp. 1223-1226
    • Lee, W.1    Wu, A.2
  • 9
    • 0042454612 scopus 로고    scopus 로고
    • "Coded modulation with low-density parity-check codes"
    • M.S. thesis, Texas A&M Univ., College Station, TX
    • R. Narayanaswami, "Coded modulation with low-density parity-check codes," M.S. thesis, Texas A&M Univ., College Station, TX, 2001.
    • (2001)
    • Narayanaswami, R.1
  • 10
    • 0033530994 scopus 로고    scopus 로고
    • "Low-density parity-check codes with semirandom parity-check matrix"
    • Jan
    • L. Ping, W. K. Leung, and N. Phamdo, "Low-density parity-check codes with semirandom parity-check matrix," Electron. Lett., vol. 35, no. 7, pp. 38-39, Jan. 1999.
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  • 13
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    • Sep
    • A. Tarable, S. Benedetto, and G. Montorsi, "Mapping interleaver laws to parallel turbo and LDPC decoder architectures," IEEE Trans. Inf. Theory, vol. 50, no. 9, pp. 2002-2009, Sep. 2004.
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.