-
1
-
-
0033697586
-
Can recursive bisection produce routable placements?
-
June
-
A. E. Caldwell, K. A. B., and M. I. L. Can recursive bisection produce routable placements? In Proc. Design Automation Conf., pages 477-482, June 2000.
-
(2000)
Proc. Design Automation Conf.
, pp. 477-482
-
-
Caldwell, A.E.1
-
4
-
-
0032026510
-
A stochastic wire-length distribution for gigascale integration (GSI) - PART I: Derivation and validation
-
March
-
J. A. Davis, V. K. De, and J. D. Meindl. A stochastic wire-length distribution for gigascale integration (GSI) -PART I: Derivation and validation. IEEE Trans. on Electron Devices, 45(3):580-589, March 1998.
-
(1998)
IEEE Trans. on Electron Devices
, vol.45
, Issue.3
, pp. 580-589
-
-
Davis, J.A.1
De, V.K.2
Meindl, J.D.3
-
5
-
-
0019565820
-
Wire length distribution for placements of computer logic
-
W. E. Donath. Wire length distribution for placements of computer logic. IBM J. of Research and Development, 25:152-155, 1981.
-
(1981)
IBM J. of Research and Development
, vol.25
, pp. 152-155
-
-
Donath, W.E.1
-
7
-
-
0015206785
-
On a pin versus block relationship for partitions of logic graphs
-
B. S. Landman and R. L. Russo. On a pin versus block relationship for partitions of logic graphs. IEEE Trans. on Comput., C-20:1469-1479, 1971.
-
(1971)
IEEE Trans. on Comput.
, vol.C-20
, pp. 1469-1479
-
-
Landman, B.S.1
Russo, R.L.2
-
10
-
-
0033358323
-
On an efficient method for estimating the interconnection complexity of designs and on the existence of region III in Rent's rule
-
March
-
D. Stroobandt. On an efficient method for estimating the interconnection complexity of designs and on the existence of region III in Rent's rule. In Proc. 9th Great Lakes Symposium on VLSI, pages 330-331, March 1999.
-
(1999)
Proc. 9th Great Lakes Symposium on VLSI
, pp. 330-331
-
-
Stroobandt, D.1
-
11
-
-
0034259516
-
Generating synthetic benchmark circuits for evaluating CAD tools
-
September
-
D. Stroobandt, P. Verplaetse, and J. Van Campenhout. Generating synthetic benchmark circuits for evaluating CAD tools. IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems., 19(9):1011-1022, September 2000.
-
(2000)
IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems
, vol.19
, Issue.9
, pp. 1011-1022
-
-
Stroobandt, D.1
Verplaetse, P.2
Van Campenhout, J.3
-
12
-
-
0023979261
-
An algorithm for quadrisection and its application to standard cell placement
-
March
-
P. Suarism and G. Kedem. An algorithm for quadrisection and its application to standard cell placement. IEEE Trans. on Circuits & Systems, 35(3):294-303, March 1988.
-
(1988)
IEEE Trans. on Circuits & Systems
, vol.35
, Issue.3
, pp. 294-303
-
-
Suarism, P.1
Kedem, G.2
-
14
-
-
0012904471
-
A stochastic model for the interconnection topology of digital circuits
-
Technical Report PARIS 00-07, Ghent University, Belgium, ELIS Department, December
-
P. Verplaetse. A stochastic model for the interconnection topology of digital circuits. Technical Report PARIS 00-07, Ghent University, Belgium, ELIS Department, December 2000. Submitted to IEEE Trans. on Very Large Scale Integration (VLSI) Systems.
-
(2000)
IEEE Trans. on Very Large Scale Integration (VLSI) Systems
-
-
Verplaetse, P.1
-
16
-
-
0033687778
-
A snap-on placement tool
-
April
-
X. Yang, M. Wang, K. Eguro, and M. Sarrafzadeh. A snap-on placement tool. In Proc. of Intl. Symp on Physical Design, pages 153-158, April 2000.
-
(2000)
Proc. of Intl. Symp on Physical Design
, pp. 153-158
-
-
Yang, X.1
Wang, M.2
Eguro, K.3
Sarrafzadeh, M.4
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