A low jitter delay-locked loop with a realignment duty cycle corrector

Proceedings - IEEE International SOC Conference

Volumn , Issue , 2005, Pages 75-76

  Li, L ^a   Chen, J Hou Ming ^a   Chang, R Chen Hao ^a  

^a NATIONAL CHUNG HSING UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; ELECTRIC POWER UTILIZATION; JITTER; WAVEFORM ANALYSIS;

DELAY-LOCKED LOOPS (DLL); REALIGNMENT DUTY CYCLE CORRECTOR (RDCC);

INTEGRATED CIRCUIT LAYOUT;

EID: 30844445046     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)

1. J. Lee and B. Kim, "A low-noise fast-lock phase-locked loop with adaptive bandwidth control," IEEE J. Solid-State Circuit, vol. 35, pp. 780-787, May 2000.
2. Y.-J. Jung, et al., "A dual-loop delay-locked loop using multiple voltage -controlled delay lines," IEEE J. Solid-State Circuit, vol. 36, pp. 784-797, May 2001.
3. J. Ye, et al., "A 0.18 /um CMOS 10-Gb/S multichannel transmitter with duty-cycle correction," International Conference on ASIC, vol. 1, pp. 21-24, Oct. 2003.
4. S. Karthikeyan, "Clock duty cycle adjuster circuit for switched capacitor circuits," Electronics Letters, vol. 38, pp. 1008-1009, Aug. 2002.
5. Y. C. Jang, S. J. Bae and H.J. Park, "CMOS digital duty cycle correction circuit for multi-phase clock," Electronics Letters, vol. 39, pp. 1383-1384, Sept. 2003.