A 0.18μm CMOS 10-Glb/S multichannel transmitter with duty-cycle correction

IEEE International Symposium on Semiconductor Manufacturing Conference Proceedings

Volumn 1, Issue , 2003, Pages 534-536

  Ye, Jinghua ^a   Guo, Gan ^a   Huang, Lin ^a   Chen, Yihui ^a   Chen, Xuefeng ^a   Hong, Zhiliang ^a  

^a FUDAN UNIVERSITY   (China)

Author keywords

Duty cycle correction (DCC); Ethernet; Linedriver; Transmitter

Indexed keywords

CLOCKS; DIGITAL STORAGE; TRANSMITTERS;

CMOS PROCESSS; DIFFERENTIAL OUTPUT; DUTY CYCLE CORRECTION; IEEE 802.3AE; MULTICHANNEL; MULTICHANNEL TRANSCEIVERS; MULTIPHASE CLOCK; PEAK-TO-PEAK;

CMOS INTEGRATED CIRCUITS;

EID: 30844432082     PISSN: 1523553X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICASIC.2003.1277604     Document Type: Conference Paper

References (5)

1. G. Ahn, D-K. Jeong, and G. Kim, "A 2-Gbaud 0.7-V swing voltage-mode driver and on-chip terminator for high-speed NRZ data transmission". IEEE JSSC, vol.35, pp915-918, Jun. 2000
2. C. Yang, Mark Horowitz, "A 0.8- m CMOS 2.5 Gb/s Oversampling Receiver and Transmitter tor Serial Links" IEEE JSSC, vol.31. pp2015-2023, Dec. 1996
3. IEEE 802.3ae Standard Spec.
4. J.G. Maneatis, "Low-Jitter Process- Independent DLL and PLL Based on Self-Biased Techniques," IEEE JSSC, vol. 31, no. 11, pp. 1723-1732, Nov. 1996.
5. M. Kurisu, M. Kaneko, and T. Suzaki, "2.8-Gb/s 176-mW byte interleaved and 3.0-Gb/s 118-mW bit-interleaved 8:1 multiplexers with a 0.15-um CMOS technology," IEEE JSSC, vol. 31, pp. 2024-2029, Dec. 1996.