CMOS digital duty cycle correction circuit for multi-phase clock

Electronics Letters

Volumn 39, Issue 19, 2003, Pages 1383-1384

  Jang, Y C ^a   Bae, S J ^a   Park, H J ^a  

^a Pohang University of Science and Technology (POSTECH)   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

ANALOG TO DIGITAL CONVERSION; CMOS INTEGRATED CIRCUITS; DYNAMIC RANDOM ACCESS STORAGE; ELECTRIC POTENTIAL; INTEGRATING CIRCUITS; TIMING CIRCUITS;

DIGITAL DUTY CYCLE CORRECTION CIRCUIT; MULTIPHASE CLOCK; TIMING DIAGRAM;

DIGITAL INTEGRATED CIRCUITS;

EID: 0141904688     PISSN: 00135194     EISSN: None     Source Type: Journal    
DOI: 10.1049/el:20030908     Document Type: Article

References (3)

1. Lee, T.H., Donnelly, K.S., Ho, J.T.C., Zerbe, J., Johnson, M.G., and Ishikawa, T.: 'A 2.5 V CMOS delay-locked loop for an 18 Mbit, 500 Megabyte/s DRAM', IEEE J. Solid-State Circuits, 1994, 29, pp. 1491-1496
2. Karthikayen, S.: 'Clock duty cycle adjuster circuit for switched capacitor circuits', Electronics Letters, 2002, 38, (18), pp. 1008-1009
3. Sidiropoulos, S., and Horowitz, M.: 'A 700-Mb/s/pin CMOS signaling interface using current integrating receivers', IEEE J. Solid-State Circuits, 1997, 32, pp. 681-690