Exploring the performance potential of itanium® processors with ILP-based scheduling

International Symposium on Code Generation and Optimization, CGO

Volumn , Issue , 2004, Pages 189-200

  Winkel, Sebastian ^a  

^a SAARLAND UNIVERSITY   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

CODE GENERATION; INSTRUCTION-LEVEL PARALLELISM (ILP); INTEGER LINEAR PROGRAMMING (ILP);

AUTOMATION; CODES (SYMBOLS); INTEGER PROGRAMMING; LINEAR PROGRAMMING; SCHEDULING; SOFTWARE ENGINEERING;

PROGRAM PROCESSORS;

EID: 3042662360     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/CGO.2004.1281674     Document Type: Conference Paper

References (23)

1. ILOG CPLEX 8.0, 2002. www.cplex.com.
2. HP Caliper, 2003. www.hp.com/go/caliper.
3. D. Alpert. Itanium Processor Status Report. Microprocessor Report, July 2003.
4. J. Bharadwaj, K. Menezes, and C. McKinsey. Wavefront Scheduling: Path Based Data Representation and Scheduling of Subgraphs. Journal of Instruction-Level Parallelism, 1(6):1-6, 2000.
5. R. E. Bixby, M. Fenelon, Z. Gu, E. Rothberg, and R. Wunderling. ILOG CPLEX Division. MIP: Theory and Practice - Closing the Gap. In M. J. D. Powell and S. Scholtes, editors, System Modelling and Optimization: Methods, Theory and Applications, pages 19-49. Kluwer, The Netherlands, 2000.
6. C.-M. Chang, C.-M. Chen, and C.-T. King. Using Integer Linear Programming for Instruction Scheduling and Register Allocation in Multi-Issue Processors. Computers and Mathematics with Applications, 34(9):1-14, Nov. 1997.
7. S. Chaudhuri, R. Walker, and J. Mitchell. Analyzing and Exploiting the Structure of the Constraints in the ILP-Approach to the Scheduling Problem. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2(4):456-471, Dec. 1994.
8. D.-Y. Chen, L. Liu, C. Fu, S. Yang, C. Wu, and R. Ju. Efficient Resource Management during Instruction Scheduling for the EPIC Architecture. In Proceedings of the PACT 2003, New Orleans, Sept. 2003.
9. G. Dantzig. Maximization of a linear function of variables subject to linear inequalities. In T. C. Koopmans, editor, Activity Analysis of Production and Allocation, pages 339-347. Wiley, New York, 1951.
10. C. Dulong, R. Krishnaiyer, D. Kulkarni, D. Lavery, W. Li, J. Ng, and D. Sehr. An Overview of the Intel® IA-64 Compiler. Intel Technology Journal, (Q4), 1999.
11. C. Gebotys and M. Elmasry. Global Optimization Approach for Architectural Synthesis. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, pages 1266-1278, 1993.
12. S. Haga and R. Barua. EPIC Instruction Scheduling Based on Optimal Approaches. Proceedings of the EPIC-1 Workshop, Dec. 2001.
13. M. Heffernan, J. Liu, and K. Wilken. Optimal Instruction Scheduling Using Integer Programming. Proceedings of the ACM SIGPLAN 2000 Conference on Programming Language Design and Implementation, pages 121-133, June 2000.
14. Intel. Intel® Itanium® Architecture Software Developer's Manual, Volume 1: Application Architecture, Oct. 2002.
15. Intel. Intel® Itanium® 2 Processor Reference Manual for Software Development and Optimization, Apr. 2003.
16. D. Kästner. Retargetable Code Optimisation by Integer Linear Programming. PhD thesis, Saarland University, 2000.
17. D. Kästner and S. Winkel. ILP-based Instruction Scheduling for IA-64. In Proceedings of the ACM SIGPLAN Workshop on Languages, Compilers and Tools for Embedded Systems, Snowbird, June 2001.
18. J. McCormick and A. Knies. A Brief Analysis of the SPEC CPU2000 Benchmarks on the Intel® Itanium® 2 Processor. HotChips 14, 2002.
19. G. Nemhauser and L. Wolsey. Integer and Combinatorial Optimization. John Wiley and Sons, New York, 1988.
20. A. Schrijver. Combinatorial Optimization: Polyhedra and Efficiency. Springer, Berlin; Heidelberg; New York, 2003.
21. T. Wilson, G. Grewal, and D. Banerji. An ILP Solution for Simultaneous Scheduling, Allocation, and Binding in Multiple Block Synthesis. In Proceedings of the International Conference on Computer Design: VLSI in Computers and Processors, pages 581-586. IEEE Computer Society Press, 1994.
22. S. Winkel. Optimal Global Scheduling for Itaniura Processor Family. In Proceedings of the EPIC-2 Workshop, Istanbul, Nov. 2002.
23. S. Winkel. Optimal Global Instruction Scheduling for the Itanium Processor Architecture. PhD thesis, Saarland University, Saarbrücken, Germany, 2004. To appear.