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Volumn 36, Issue 8, 2001, Pages 145-154

ILP-based instruction scheduling for IA-64

Author keywords

[No Author keywords available]

Indexed keywords


EID: 2942747557     PISSN: 03621340     EISSN: None     Source Type: Journal    
DOI: 10.1145/384196.384217     Document Type: Article
Times cited : (16)

References (25)
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    • Georgia Institute of Technology, School of Industrial and Systems Engineering, Atlanta, CA 30332-0205, Jan.
    • E. Johnson, G. Nemhauser, and M. Savelsbergh, "Progress in Integer Programming: An Exposition," Tech. Rep. LEC-97-02, Georgia Institute of Technology, School of Industrial and Systems Engineering, Atlanta, CA 30332-0205, Jan. 1997. http://tli.isye.gatech.edu/reports.html.
    • (1997) Tech. Rep. LEC-97-02
    • Johnson, E.1    Nemhauser, G.2    Savelsbergh, M.3
  • 4
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    • Integer Programming
    • G. Nemhauser, A. R. Kan, and M. Todd, eds., ch. VI, Amsterdam; New York; Oxford: North-Holland
    • G. Nemhauser and L. Wolsey, "Integer Programming," in Handbooks in Operations Research and Management Science (G. Nemhauser, A. R. Kan, and M. Todd, eds.), ch. VI, pp. 447-527, Amsterdam; New York; Oxford: North-Holland, 1989.
    • (1989) Handbooks in Operations Research and Management Science , pp. 447-527
    • Nemhauser, G.1    Wolsey, L.2
  • 14
    • 2342662014 scopus 로고
    • Synthesis of Domain Specific Multiprocessor Systems including Memory Design
    • New York, IEEE Press
    • A. Bachmann, M. Schöbinger, and L. Thiele, "Synthesis of Domain Specific Multiprocessor Systems including Memory Design," in VLSI Signal Processing VI, (New York), pp. 417-425, IEEE Press, 1993.
    • (1993) VLSI Signal Processing VI , pp. 417-425
    • Bachmann, A.1    Schöbinger, M.2    Thiele, L.3
  • 17
    • 0022151809 scopus 로고
    • An Optimal Instruction Scheduling Model for a Class of Vector Processors
    • Nov.
    • S. Arya, "An Optimal Instruction Scheduling Model for a Class of Vector Processors," IEEE Transactions on Computers, vol. C-34, Nov. 1985.
    • (1985) IEEE Transactions on Computers , vol.C-34
    • Arya, S.1
  • 21
    • 3242806053 scopus 로고    scopus 로고
    • Wavefront Scheduling: Path Based Data Representation and Scheduling of Subgraphs
    • J. Bharadwaj and C. McKinsey, "Wavefront Scheduling: Path Based Data Representation and Scheduling of Subgraphs," Journal of Instruction-Level Parallelism, vol. 1, no. 6, pp. 1-6, 2000.
    • (2000) Journal of Instruction-Level Parallelism , vol.1 , Issue.6 , pp. 1-6
    • Bharadwaj, J.1    McKinsey, C.2
  • 23
    • 0003782477 scopus 로고
    • On Predicated Execution
    • Hewlett-Packard Laboratories, Palo Alto CA, May
    • J. Park and M. Schlansker, "On Predicated Execution," Tech. Rep. HPL-91-58, Hewlett-Packard Laboratories, Palo Alto CA, May 1991.
    • (1991) Tech. Rep. HPL-91-58
    • Park, J.1    Schlansker, M.2
  • 25
    • 0003335468 scopus 로고    scopus 로고
    • The Computation of Transcendental Functions on the IA-64 Architecture
    • J. Harrison, T. Kubaska, S. Story, and P. Tang, "The Computation of Transcendental Functions on the IA-64 Architecture," Intel Technology Journal, vol. Q4, 1999.
    • (1999) Intel Technology Journal , vol.Q4
    • Harrison, J.1    Kubaska, T.2    Story, S.3    Tang, P.4


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.