Electrical characterization of model-based dummy feature insertion in Cu interconnects

IEEE International Conference on Microelectronic Test Structures

Volumn , Issue , 2004, Pages 87-92

  Doong, Kelvin Y Y ^a   Lin, K C ^a   Tseng, T C ^a   Lu, Y C ^a   Lin, S C ^a   Hung, L J ^a   Ho, P S ^a   Hsieh, Sunnys ^a   Young, K L ^a   Liang, M S ^a  

^a Taiwan Semiconduct Mfg C Shinchu   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; CAPACITANCE; CHEMICAL MECHANICAL POLISHING; COPPER; ELECTRIC RESISTANCE; METALLIZING; MICROPROCESSOR CHIPS; SILICA;

ELECTRICAL CHARACTERIZATION; NON-LINEAR OPTIMIZATION PROBLEMS;

OPTICAL INTERCONNECTS;

EID: 3042611498     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (14)

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