Design guide and process quality improvement for treatment of device variations in an LSI chip

IEEE International Conference on Microelectronic Test Structures

Volumn , Issue , 2004, Pages 201-206

  Aoki, Masakazu ^a,b   Ohkawa, Shin Ichi ^a   Masuda, Hiroo ^a  

^a Semiconduct Technol Acad Res C   (Japan)

^b TOKYO UNIVERSITY OF SCIENCE   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITORS; COMPUTER AIDED DESIGN; GATES (TRANSISTOR); LOGIC GATES; MATHEMATICAL MODELS; MICROPROCESSOR CHIPS; POLYSILICON; TRANSISTORS;

DEVICE MATRIX ARRAY (DMA); MEASUREMENT ARRAY UNIT (MAU); POLY-SI GATE;

LSI CIRCUITS;

EID: 3042557825     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (8)

1. TAU 2002 Workshop, Proceedings, Dec. 2002.
2. D. Boning, J. Panganiban, K. Gonzalez-Valentin, S. Nassif, C. MacDowell, A. Gattiker, and F. Liu, "Test structures for delay variability," ibid., p. 109.
3. S. Ohkawa, M. Aoki, and H. Masuda., "Analysis and characterization of device variations in an LSI chip using an integrated Device Matrix Array," ICMTS, Proc., pp.70-75, Mar. 2003.
4. M. J. M. Pelgrom, A. C. J. Duinmaijer, and A. P. G. Weibers, "Matching properties of MOS transistors," IEEE J. Solid-State Circuits, Vol. 24, pp. 1433-1440, Oct. 1989.
5. D. Bumett, K. Erington, C. Subramanian, and K. Baker, "Implication of fundamental threshold voltage variations for high-density SRAM and logic circuits," Symp. VLSI Technology. Technical Digest, pp. 15-16, June. 1994.
6. A. Agarwal, D. Blaauw, V. Zolotov, S. Sundareswaran, M. Zhao, K. Gala, and R. Panda, "Statistical delay computation considering special correlations," ASP-DAC, Proc. pp.271-276, Jan. 2003.
7. J. C. Chen, D. Sylvester, C. Hu, H. Aoki, S. Nakagawa, and S.-Y. Oh. "An on-chip, interconnect capacitance characterization method with sub-femto-farad resolution," ICMTS. Proc. pp.77-80, Mar. 1997.
8. B. E. Stine, D. S. Boning, and J. E. Chung, "Analysis and decomposition of spatial variation in integrated circuit processes and devices." IEEE Trans. on Semiconductor Manufacturing. Vol. 10, pp. 24-41, Feb. 1997.