Analysis and characterization of device variations in an LSI chip using an integrated device matrix array

IEEE International Conference on Microelectronic Test Structures

Volumn , Issue , 2003, Pages 70-75

  Ohkawa, Shin Ichi ^a   Aoki, Masakazu ^a   Masuda, Hiroo ^a  

^a SEMICONDUCTOR TECHNOLOGY ACADEMIC RESEARCH CENTER   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; CMOS INTEGRATED CIRCUITS; ELECTRIC RESISTANCE MEASUREMENT; MOSFET DEVICES; SWITCHING CIRCUITS;

DEVICE MATRIX ARRAY (DMA);

LSI CIRCUITS;

EID: 0037966389     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)

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2. G. Ono, M. Miyazaki and K. Ishibashi, "Quantitative Study of an SA-Vt CMOS Circuit: Evaluation of Fluctuation in Device and Circuit Performance," SSDM, Extended Abstract, pp.374-375, Aug. 2000.
3. S. R. Nassif, "Impact of Manufacturing Variability on Delay," Microprocessor Design Workshop, ISSCC, Feb. 2002.
4. Y. Shimizu, M. Nakamura, T. Matsuoka and K. Taniguchi, "Test Structure for Precise Statistical Characteristics Measurement of MOSFETs," ICMTS, Proc. p.49-54, Apr. 2002.
5. J. C. Chen, D. Sylvester, C. Hu, H. Aoki, S. Nakagawa, S.-Y. Oh, "An On-Chip, Interconnect Capacitance Characterization Method with Sub-Femto-Farad Resolution," ICMTS, Proc. pp.77-80, Mar. 1997.