Fabrication of 50-nm gate SOI n-MOSFETs using novel plasma-doping technique

IEEE Electron Device Letters

Volumn 25, Issue 6, 2004, Pages 366-368

  Cho, Won Ju ^a   Ahn, Chang Geun ^a   Im, Kiju ^a   Yang, Jong Heon ^a   Oh, Jihun ^a   Baek, In Bok ^a   Lee, Seongjae ^a  

^a Electronics and Telecommunications Research Institute (ETRI)   (South Korea)

Author keywords

Elevated temperature; Low damage; MOSFETs; Nanoscale; Plasma doping; Silicon on insulator (SOI); Tri gate structure

Indexed keywords

GATES (TRANSISTOR); PLASMA APPLICATIONS; SEMICONDUCTOR DEVICE MANUFACTURE; SEMICONDUCTOR DOPING; SILICON ON INSULATOR TECHNOLOGY; THERMAL EFFECTS;

DOPANTS; PLASMA DOPING; SHORT CHANNEL EFFECTS; TRIGATE STRUCTURE;

MOSFET DEVICES;

EID: 2942746700     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/LED.2004.829007     Document Type: Letter

References (9)

1. J. P. Colinge, Silicon-on-Insulator Technology: Materials to VLSI. Norwell, MA: Kluwer, 1991.
2. D. J. Shahidi, C. A. Anderson, B. A. Chappell, T. I. Chappell, J. H. Comfort, B. Davari, R. H. Dennard, R. L. French, P. A. MacFarland, J. S. Neely, T. H. Ning, M. R. Polcari, and J. D. Warnock, "A room-temperature 0.1 μm CMOS on SOI," IEEE Trans. Electron Devices, vol. 41, pp. 2405-2412, Dec., 1994.
3. + junction formation using plasma immersion ion implantation for CMOS technology," in Symp. VLSI Tech. Dig., 2001, pp. 21-22.
4. D. Lenoble, A. Halimaoui, O. Kermarrec, Y. Campidelli, D. Bensahel, J. Bonnouvrier, O. Menut, E. Robilliart, E. Perrin, F. Arnaud, F. Boeuf, T. Skotnicki, A. Grouilett, and G. Bignell, "Integration of ultrashallow junctions in sub-0.1 μm CMOS transistors: What kind of process for a "safe" advanced technology?," in Proc. Int. Workshop Junction Tech., 2001, pp. 29-34.
5. W.-J. Cho, J.-H. Yang, K. Im, J. Ph, and S. Lee, "Fabrication and process simulation of SOI MOSFETs with a 30-nm gate length," J. Korean Phys. Soc., vol. 43, pp. 892-897, 2003.
6. N. Q. Liem, T. T. K. Chi, D. X. Thanh, N. D. Sinh, F. Falk, G. Andra, E. Ose, and J. Bergmann, "Raman study of stresses in laser-crystallized Si films on glass," in Proc. Fifth Vietnamese/German Seminar Physics Engineering, 2001, pp. 1-4.
7. C. Droz, E. Vallat-Sauvain, J. Bailet, L. Feitkecht, and A. Shah, "Application of RAMAN spectroscopy for the microstructure characterization in microcrystalline silicon solar cells," in Proc. Eur. Photovoltaic Solar Energy Conf., 2001, pp. 2917-2920.
8. S. M. Sze, VLSI Technology, 2nd ed. New York: McGraw-Hill, 1988, p. 343.
9. B. S. Doyle, S. Datta, M. Doczy, S. Hareland, B. Jin, J. Kavalieros, T. Linton, A. Murthy, R. Rios, and R. Chau, "High performance fully-depleted tri-gate CMOS transistors," IEEE Electron Device Lett., vol. 24, pp. 263-265, Mar. 2003.