Shallow n+/p+ junction formation using plasma immersion ion implantation for CMOS technology

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue TECHNOLOGY SYMP., 2001, Pages 21-22

  Lee, K ^a   Sim, J H ^a   Li, Y ^a   Kang, W T ^a   Malik, R ^a   Rengarajan, R ^a   Chaloux, S ^a   Bernstein, J ^a   Kellerman, P ^a  

^a IBM   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; GATES (TRANSISTOR); ION IMPLANTATION; MOSFET DEVICES; PLASMAS; THRESHOLD VOLTAGE;

PLASMA IMMERSIONS;

SEMICONDUCTOR JUNCTIONS;

EID: 0034794353     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)