Integration of ultra-shallow junctions in sub-0.1 μm CMOS transistors: What kind of process for a "safe" advanced technology?

Extended Abstracts of the 2nd International Workshop on Junction Technology, IWJT 2001

Volumn , Issue , 2001, Pages 29-34

  Lenoble, D ^a   Halimaoui, A ^a   Kermarrec, O ^a   Campidelli, Y ^a   Bensahel, D ^a   Bonnouvrier, J ^a   Menut, O ^a   Robilliart, E ^a   Perrin, E ^a   Arnaud, F ^a   Boeuf, F ^a   Skotnicki, T ^a   Grouillet, A ^b   Bignell, G ^a  

^a STMICROELECTRONICS   (France)

^b ORANGE LABS   (France)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC RESISTANCE; ION IMPLANTATION; NANOTECHNOLOGY; RAPID THERMAL ANNEALING;

ADVANCED TECHNOLOGY; ANOMALOUS DIFFUSION; CONVENTIONAL APPROACH; INTEGRATION PROCESS; INTERNATIONAL TECHNOLOGY; STANDARD ARCHITECTURE; SUB-100 NM TECHNOLOGIES; ULTRA SHALLOW JUNCTION;

LITHOGRAPHY;

EID: 84963755513     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IWJT.2001.993820     Document Type: Conference Paper

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