Patterning sub-50 nm Fin-FET using KrF lithography tool

Proceedings of SPIE - The International Society for Optical Engineering

Volumn 5379, Issue , 2004, Pages 260-267

  Singh, Navab ^a   Jagar, S ^a   Mehta, Sohan Singh ^a   Roy, Moitreyee Mukherjee ^a   Kumar, Rakesh ^a   Balasubramanian, N ^a  

^a INSTITUTE OF MICROELECTRONICS   (Singapore)

Author keywords

APSM; CLM; DEWS; Fin FET; Patterning Fin; Phase shift lithography

Indexed keywords

CHROME-LESS MASK (CLM) TECHNIQUES; DUAL EXPOSURE WITH SHIFT (DEWS); FIN FET; PATTERNING FIN; PHASE SHIFT LITHOGRAPHY;

CMOS INTEGRATED CIRCUITS; ELECTRIC CONDUCTANCE; GATES (TRANSISTOR); LITHOGRAPHY; PARAMETER ESTIMATION; TRANSISTORS;

PHASE SHIFT;

EID: 2942668264     PISSN: 0277786X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1117/12.536040     Document Type: Conference Paper

References (5)

1. Hisamoto et al., "A self aligned double gate MOSFET scalable to 20 nm", IEEE Transactions on Electron Devices, vol. 47, no. 12, Dec 2000 pp. 2320-2324
2. Huang et al., "Sub 50-nm p-channel FinFET", IEEE TED, Vol 48, no 5, May 2001, pp. 880-886.
3. Hisamoto et al., "A folded-channel MOSFET for deep-sub-tenth micron era," 1998 IEEE IEDM pp. 1032-34.
4. Nick Lindert et al., "Sub-60nm quasi planner FinFET fabricated using a simplified process", IEEE Electron Device Letters, vol. 22, no. 10, Oct 2001, pp 487-489.
5. Choi et al., "Nano scale CMOS spacer FinFET for the terabit era", IEEE Electron Device Letters, vol 23. no. 1. Jan 2002 pp 25-27.