Power-aware branch prediction techniques: A compiler-hints based approach for VLIW processors

Proceedings of the ACM Great Lakes Symposium on VLSI

Volumn , Issue , 2004, Pages 440-443

  Monchiero, M ^a   Palermo, G ^a   Sami, M ^a   Silvano, C ^a   Zaccaria, V ^b   Zafalon, R ^b  

^a POLITECNICO DI MILANO   (Italy)

^b STMICROELECTRONICS   (Italy)

Author keywords

Branch Prediction; Low Power Design; VLIW Processors

Indexed keywords

COMPUTER ARCHITECTURE; COMPUTER HARDWARE; COMPUTER SIMULATION; ELECTRIC FILTERS; ENERGY DISSIPATION; PROGRAM COMPILERS; PROGRAM PROCESSORS;

BRANCH PREDICTION; FILTERING EFFICACY; LOW POWER DESIGN;

VERY LONG INSTRUCTION WORD ARCHITECTURE;

EID: 2942657958     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (11)

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