Branch prediction techniques for low-power VLIW processors

Proceedings of the IEEE Great Lakes Symposium on VLSI

Volumn , Issue , 2003, Pages 225-228

  Palermo, G ^a,b   Sami, M ^a   Silvano, C ^a   Zaccaria, V ^a   Zafalon, R ^b  

^a POLITECNICO DI MILANO   (Italy)

^b STMICROELECTRONICS   (Italy)

Author keywords

Branch Prediction; Low Power Design; VLIW Processors

Indexed keywords

COMPUTER HARDWARE; ENERGY EFFICIENCY; OPTIMIZATION; PRODUCT DESIGN;

BRANCH PREDICTION TECHNIQUES;

VERY LONG INSTRUCTION WORD ARCHITECTURE;

EID: 0038375768     PISSN: 10661395     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/764863.764866     Document Type: Conference Paper

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