From STG to extended-burst-mode machines

Proceedings - International Symposium on Asynchronous Circuits and Systems

Volumn , Issue , 1999, Pages 145-158

  Beister, J ^a   Eckstein, G ^a   Wollowski, R ^a  

^a University of Koblenz Landau   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

ASYNCHRONOUS DESIGN; BURST-MODE; CIRCUIT MODELS; FINITE STATE MACHINES; INPUT AND OUTPUTS; INPUT-OUTPUT; OUTPUT PARTITIONING; SIGNAL TRANSITION GRAPHS;

SPECIFICATIONS;

EID: 2942665574     PISSN: 15228681     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASYNC.1999.761530     Document Type: Conference Paper

References (13)

1. S. H. Unger. Asynchronous Sequential Switching Circuits. R. E. Krieger, reprint 1983 (original edition 1969).
2. L. Lavagno and A. Sangiovanni-Vincentelli. Algorithms for synthesis and testing of asynchronous circuits. Kluwer Academic Publishers, 1993.
3. T.-A. Chu. Synthesis of Self-timed VLSI Circuits from Graph-theoretic Specifications. PhD thesis, MIT, 1987.
4. J. Cortadella, M. Kishinevsky, A. Kondratyev, L. Lavagno, and A. Yakovlev. Complete state encoding based on the theory of regions. In Proc. of the 2nd Int. Symp. on Advanced Research in Asynchronous Circuits and Systems, Aizu, March 1996.
5. P. Kudva, H. Jacobson, G. Gopalakrishnan. A Technique for Synthesizing Distributed Burst-mode Circuits. In Proc. of the 33rd DAC, Los Alamitos, 1996.
6. S. M. Nowick. Automatic Synthesis of Burst-Mode Asynchronous Controllers. PhD thesis, Stanford Univ., 1993.
7. K. Y. Yun. Synthesis of Asynchronous Controllers for Heterogeneous Systems. PhD thesis, Stanford Univ., 1994.
8. A. Davis, B. Coates, and K. Stevens. The Post Office Experience: Designing a Large Asynchronous Chip. Proc. 26th Annu. Hawaii Int. Conf. on Systems Sciences, vol. 1,1993.
9. J. Cortadella, L. Lavagno, P. Vanbekbergen and A. Yakovlev. Designing asynchronous circuits from behavioural specifications with internal conflicts. UPC/DAC Technical Report no. RR 94/08.
10. R. Wollowski and J. Beister. Precise Petri Net Modelling of Critical Races in Asynchronous Arbiters and Synchronizers. In Proc. of the workshop on Hardware Design and Petri Nets (HWPN), Lisbon, 1998.
11. R. Wollowski. Entwurfsorientierte Petrinetz-Modellierung des Schnittstellen-Sollverhaltens asynchroner Schaltwerksverbünde. Dissertation, Univ. of Kaiserslautem, 1997, (published by Shaker Verlag, Aachen, 1997).
12. G. de Micheli. Synthesis and optimization of digital circuits. McGraw-Hill, Inc., 1995.
13. A. Grasselli and F. Luccio. A method for combined row-column reduction of flow tables. Proc. 7th Ann. Symp. Switching Theory, Automata, 1966.