Test set enhancement for quality transition faults using function-based methods

Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI

Volumn , Issue , 2005, Pages 182-187

  Neophytou, Stelios ^a   Michael, Maria K ^a   Tragoudas, Spyros ^b  

^a UNIVERSITY OF CYPRUS   (Cyprus)

^b SOUTHERN ILLINOIS UNIVERSITY   (United States)

Author keywords

ATPG; Critical Paths; Delay Test; High Quality Test; Test Compaction; Transition Fault

Indexed keywords

ACTIVATION ANALYSIS; TEST FACILITIES; VECTORS; VLSI CIRCUITS;

ATPG; CRITICAL PATHS; DELAY TEST; HIGH QUALITY TEST; TEST COMPACTION;

NETWORKS (CIRCUITS);

EID: 29244456474     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1057661.1057706     Document Type: Conference Paper

References (11)

1. D. Bhattacharya, P. Agrawal and V.D. Agrawal, "Test Pattern Generation for Path Delay Faults using Binary Decision Diagrams", IEEE Trans. on Computers, Vol. 44, No. 3, pp. 434-447, Mar. 1995.
2. R. Bryant, "Graph-based algorithms for boolean function manipulation", IEEE Trans. on Computers,Vol. C-35, No. 8, pp. 677-691, Aug. 1986.
3. K.T. Cheng and H.C. Chen, "Classification and Identification of Nonrobust Untestable Path Delay Faults",IEEE Trans. on CAD, Vol. 15, pp. 845-853, Aug. 1996.
4. I. Hamzaoglu and J.H. Patel, "Compact two-pattern test set generation for combinational and full scan circuits", Proc. ITC, pp. 944-953, 1998.
5. A. Krstic, K. T. Cheng, Delay Fault Testing for VLSI Circuits, Kluwer Academic Publishers, Boston, MA, 1998.
6. Y. Levendel and P.R. Menon, "Transition Faults in Combinational Circuits: Input Transition Test Generation and Fault Simulation", Proc. FTCS, pp. 278-283, July 1986.
7. M.K. Michael, S. Neophytou and S. Tragoudas, "Functions for Quality Transition Fault Tests", Proc. ISQED, Mar. 2005.
8. M.H. Schulz and F. Brglez, "Accelerated Transition Fault Simulation", Proc. DAC, pp. 237-243, June 1987.
9. Y. Shao, I. Pomeranz, and S.M. Reddy, "On Generating High Quality Tests for Transition Faults", Proc. 11th. ATS, pp. 1-8, 2002.
10. F. Somenzi, "CUDD: CU Decision Diagram Package", Dept. of ECE, The University of Colorado, release 2.3.0, 1999.
11. K. Yang, K.T. Cheng, and L.C. Wang, "TranGen: A SAT-Based ATPG for Path-Oriented Transition Faults", Proc. SPDAC, 2004.