메뉴 건너뛰기




Volumn , Issue , 2005, Pages 47-54

Delay insertion method in clock skew scheduling

Author keywords

Clock skew; Delay insertion; Linear programming; Optimization; Re convergent paths

Indexed keywords

ALGORITHMS; DELAY CIRCUITS; LINEAR PROGRAMMING; OPTIMIZATION; PARAMETER ESTIMATION; TOPOLOGY;

EID: 29144466710     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1055137.1055149     Document Type: Conference Paper
Times cited : (15)

References (20)
  • 3
    • 0024628569 scopus 로고
    • On the calculation of optimal clocking parameters in synchronous circuits with level-sensitive latches
    • March
    • M. R. Dagenais and N. C. Rumin. On the calculation of optimal clocking parameters in synchronous circuits with level-sensitive latches. IEEE Transactions on Computer-Aided Design, CAD-8(3):268-278, March 1989.
    • (1989) IEEE Transactions on Computer-Aided Design , vol.CAD-8 , Issue.3 , pp. 268-278
    • Dagenais, M.R.1    Rumin, N.C.2
  • 4
    • 0025464163 scopus 로고
    • Clock skew optimization
    • July
    • J. P. Fishburn. Clock skew optimization. IEEE Transactions on Computers, C-39(7):945-951, July 1990.
    • (1990) IEEE Transactions on Computers , vol.C-39 , Issue.7 , pp. 945-951
    • Fishburn, J.P.1
  • 8
    • 0033716179 scopus 로고    scopus 로고
    • Time borrowing in high-speed functional units using skew-tolerant domino circuits
    • May
    • G. Jung, V. Perepelitsa, and G. E. Sobelman. Time borrowing in high-speed functional units using skew-tolerant domino circuits. Proceedings of the IEEE ISCAS 2000, pages 641-644, May 2000.
    • (2000) Proceedings of the IEEE ISCAS 2000 , pp. 641-644
    • Jung, G.1    Perepelitsa, V.2    Sobelman, G.E.3
  • 10
    • 0030145050 scopus 로고    scopus 로고
    • A timing analysis algorithm for circuits with level-sensitive latches
    • May
    • J. Lee, D. T. Tang, and C. K. Wong. A timing analysis algorithm for circuits with level-sensitive latches. IEEE Transactions on Computer-Aided Design, CAD-15(5):535-543, May 1996.
    • (1996) IEEE Transactions on Computer-Aided Design , vol.CAD-15 , Issue.5 , pp. 535-543
    • Lee, J.1    Tang, D.T.2    Wong, C.K.3
  • 15
  • 17
    • 1342315485 scopus 로고    scopus 로고
    • Linear timing analysis of soc synchronous circuits with level-sensitive latches
    • September
    • B. Taskin and I. S. Kourtev. Linear timing analysis of soc synchronous circuits with level-sensitive latches. In Proceedings of the 2002 IEEE ASIC/SOC Conference, pages 358-362. September 2002.
    • (2002) Proceedings of the 2002 IEEE ASIC/SOC Conference , pp. 358-362
    • Taskin, B.1    Kourtev, I.S.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.