A 6.5 GHz 130 nm single-ended dynamic ALU and instruction-scheduler loop

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2002, Pages 410-411+477+409

  Anders, Mark ^a   Mathew, Sanu ^a   Bloechel, Brad ^a   Thompson, Scott ^a   Krishnamurthy, Ram ^a   Soumyanath, K ^a   Borkar, Shekhar ^a  

^a INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ADDERS; CMOS INTEGRATED CIRCUITS; DIGITAL ARITHMETIC; JITTER; MOS DEVICES; MULTIPLEXING EQUIPMENT; PROGRAM PROCESSORS; SIGNAL GENERATORS; SPURIOUS SIGNAL NOISE;

ARITHMETIC LOGIC UNIT (ALU);

LOGIC CIRCUITS;

EID: 0036113806     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)

1. A 0.18 μm CMOS IA32 microprocessor with a 4 GHz integer execution unit
2. A 5 GHz integer execution core in 130 nm CMOS
3. Sub-500 ps ALUs in 0.18 μm SOI/Bulk CMOS: Design and scaling trends