Sub-500ps 64b ALUs in 0.18μm SOI/bulk CMOS: Design & scaling trends

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2001, Pages 318-319+460

  Mathew, S ^a   Krishnamurthy, R ^a   Anders, M ^a   Rios, R ^a   Mistry, K ^a   Soumyanath, K ^a  

^a INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ADDERS; INTEGRATED CIRCUIT LAYOUT; LOGIC CIRCUITS; LOGIC DESIGN; LOGIC GATES; MOSFET DEVICES; MULTIPLEXING; OPTIMIZATION; SILICON ON INSULATOR TECHNOLOGY;

ARITHMETIC LOGIC UNITS;

CMOS INTEGRATED CIRCUITS;

EID: 17944395754     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)

1. Fast area-efficient VLSI adders
2. 100nm Gate length high performance/low power CMOS transistor structures
3. Scalability revisited: 100nm PD-SOI transistors and implications for 50nm devices
4. nd generation 440ps SOI 64b adder
5. A 670ps, 64b dynamic low power adder design