eXtended block cache

IEEE High-Performance Computer Architecture Symposium Proceedings

Volumn , Issue , 2000, Pages 61-70

  Jourdan, Stephan ^a   Rappoport, Lihu ^a   Almog, Yoav ^a   Erez, Mattan ^a   Yoaz, Adi ^a   Ronen, Ronny ^a  

^a INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; DATA STRUCTURES; DECODING; PROGRAM PROCESSORS; REDUCED INSTRUCTION SET COMPUTING; STORAGE ALLOCATION (COMPUTER);

BRANCH MISPREDICTIONS; CACHE MISSES; EXTENDED BLOCK CACHE; TRACE CACHE;

CACHE MEMORY;

EID: 0034581530     PISSN: 15300897     EISSN: None     Source Type: Journal    
DOI: 10.1109/HPCA.2000.824339     Document Type: Article

References (14)

1. The block-based trace cache
2. Optimization of instruction fetch mechanisms for high issue rates
3. Control flow prediction with tree-like subgraphs for superscalar processors
4. Alternative fetch and issue policies for the trace cache fetch mechanism
5. Performance evaluation of a decoded instruction cache for variable-length computers
6. Path-based next trace prediction
7. Combining branch predictors
8. Exploring instruction-fetch bandwidth requirement in wide-issue superscalar processors
9. Improving trace cache effectiveness with branch promotion and trace packing
10. Dynamic flow instruction cache memory organized around trace segments independent of virtual address line
11. A scalable front-end architecture for fast instruction delivery
12. Trace cache: A low latency approach to high bandwidth instruction fetching
13. Multiple-block ahead branch predictors
14. Increasing the instruction fetch rate via multiple branch prediction and a branch address cache