Branch predictor prediction: A power-aware branch predictor for high-performance processors

Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors

Volumn , Issue , 2002, Pages 458-461

  Baniasadi, Amirali ^a   Moshovos, Andreas ^a  

^a Northwestern University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BUFFER STORAGE; PERFORMANCE; SIGNAL FILTERING AND PREDICTION; SYSTEMS ANALYSIS;

BRANCH PREDICTOR PREDICTION; HIGH-PERFORMANCE PROCESSORS;

PROGRAM PROCESSORS;

EID: 0036395516     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (3)

1. D. Parikh, K. Skadron, Y. Zhang, M. Barcella, and M.R. Stan. Power Issues Related to Branch Prediction. In Proc. Intl. Symposium on High-Performance Computer Architecture, February 2002.
2. A. Baniasadi, A. Moshovos, Instruction Flow-Based Front-end Throttling for Power-Aware High-Performance Processors. In Proc. ISLPED'01, August 2001
3. D. Brooks, V. Tiwari M. Martonosi "Wattch: A Framework for Architectural-Level Power Analysis and Optimizations", Proc of the 27th Int'l Symp. on Computer Architecture, 2000