An on-chip signal suppression countermeasure to power analysis attacks

IEEE Transactions on Dependable and Secure Computing

Volumn 1, Issue 3, 2004, Pages 179-188

  Ratanpal, Girish B ^a   Williams, Ronald D ^a   Blalock, Travis N ^a  

^a University of Virginia   (United States)

Author keywords

Code breaking; DES; Power analysis attacks; Security and protection; Smartcards; VLSI

Indexed keywords

ALGORITHMS; CODES (SYMBOLS); COMMUNICATION CHANNELS (INFORMATION THEORY); CRYPTOGRAPHY; ELECTROMAGNETIC WAVE ATTENUATION; NATURAL FREQUENCIES; POWER ELECTRONICS; SECURITY OF DATA; SMART CARDS; VLSI CIRCUITS;

CODE BREAKING; DIFFERENTIAL POWER ANALYSIS (DPA); POWER ANALYSIS ATTACKS; SECURITY AND PROTECTION; VLSI;

SIGNAL DISTORTION;

EID: 21944448367     PISSN: 15455971     EISSN: None     Source Type: Journal    
DOI: 10.1109/TDSC.2004.25     Document Type: Article

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