Mixed-scaling-rotation CORDIC (MSR-CORDIC) algorithm and architecture for high-performance vector rotational DSP applications

IEEE Transactions on Circuits and Systems I: Regular Papers

Volumn 52, Issue 11, 2005, Pages 2385-2396

  Lin, Chih Hsiu ^a   Wu, An Yeu ^a  

^a NATIONAL TAIWAN UNIVERSITY   (Taiwan)

Author keywords

Coordinate rotational digital computer (CORDIC); Extend elementary angle set (EEAS) CORDIC; Fast Fourier transform (FFT); Twiddle factor

Indexed keywords

ALGORITHMS; COMPUTER SIMULATION; DIGITAL SIGNAL PROCESSING; FAST FOURIER TRANSFORMS; ITERATIVE METHODS; SIGNAL TO NOISE RATIO; STATISTICAL METHODS;

COORDINATE ROTATIONAL DIGITAL COMPUTER (CORDIC); EXTEND ELEMENTARY ANGLE SET; TWIDDLE FACTOR;

DIGITAL COMPUTERS;

EID: 28444440286     PISSN: 10577122     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCSI.2005.853908     Document Type: Article

References (30)

1. J. E. Volder, "The CORDIC trigonometric computing technique," IRE Trans. Electron. Comput., vol. EC-8, pp. 330-334, 1959.
2. J. C. Chih and S. G. Chen, "A fast CORDIC algorithm based on a novel angle recoding scheme," in Proc 2000 IEEE Int. Symp. Circuits Syst., vol. 4, pp. 621-624.
3. C. S. Wu and A. Y. Wu, "Modified vector rotational CORDIC (MVR-CORDIC) algorithm and architecture," IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 48, no. 6, pp. 548-561, Jun. 2001.
4. A. Y. Wu and C. S. Wu, "A unified view for vector rotational CORDIC algorithms and architectures based on angle quantization approach," IEEE Trans. Circuits Syst. I, Fundam. Theory Appl., vol. 49, no. 10, pp. 1442-1456, Oct. 2002.
5. C. S. Wu, A. Y. Wu, and C. H. Lin, "A high-performance/low-latency vector rotational CORDIC architecture based on extended elementary angle set and trellis-based searching schemes," IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 50, no. 9, pp. 589-601, Sep. 2003.
6. Y. H. Hu, "The quantization effects of the CORDIC algorithm," IEEE Trans. Signal Process., vol. 40, no. 4, pp. 834-844, Apr. 1992.
7. A. M. Despain, "Fourier transform computers using CORDIC iterations," IEEE Trans. Comput., vol. 23, no. 10, pp. 993-1001, Oct. 1974.
8. M. D. Ercegovac and T. Lang, "Redundant and on-line CORDIC: Application to matrix triangularization and SVD," IEEE Trans. Comput., vol. 39, no. 6, pp. 725-740, Jun. 1990.
9. G. J. Hekstra and E. F. A. Deprettere, "Fast rotations: Low-cost arithmetic methods for orthonormal rotation," in Proc. 13th IEEE Symp. Comput. Arithmetic, 1997, pp. 116-125.
10. M. Jun, K. K. Parhi, and E. F. Deprettere, "Annihilation-reordering look-ahead pipelined CORDIC-based RLS adaptive filters and their application to adaptive beamforming," IEEE Trans. Signal Process., vol. 48, no. 8, pp. 2414-2431, Aug. 2000.
11. G. Lijun and K. K. Parhi, "Hierarchical pipelining and folding of QRD-RLS adaptive filters and its application to digital beamforming," IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 47, no. 12, pp. 1503-1519, Dec. 2000.
12. P. P. Vaidyanathan, "A unified approach to orthogonal digital filters and wave digital filters based on the LBR two-pair extraction," IEEE Trans. Circuits Syst., vol. CAS-32, no. 7, pp. 673-686, Jul. 1985.
13. A. Y. Wu, K. J. R. Liu, and A. Raghupathy, "System architecture of an adaptive reconfigurable DSP computing engine," IEEE Trans. Circuits Syst. Video Technol., vol. 8, no. 2, pp. 54-73, Feb. 1998.
14. E. F. Deprettere, P. Dewilde, and R. Udo, "Pipelined CORDIC architectures for fast VLSI filtering," in Proc. IEEE Int. Conf. ASSP, 1984, pp. 1-4.
15. L. W. Chang and S. W. Lee, "Systolic arrays for the discrete Hartley transform," IEEE Trans. Signal Process., vol. 29, no. 11, pp. 2411-2418, Nov. 1991.
16. W. H. Chen, C. H. Smith, and S. C. Fralick, "A fast computational algorithm for the discrete cosine transform," IEEE Trans. Commun., vol. COM-25, no. 9, pp. 1004-1009, Sep. 1977.
17. Y. H. Hu and S. Naganathan, "Efficient implementation of the Chirp Z-transform using a CORDIC processor," IEEE Trans. Acoust., Speech, Signal Process., vol. 38, no. 2, pp. 352-354, Feb. 1990.
18. Y. H. Hu and S. Naganathan, "An angle recoding method for CORDIC algorithm implementation," IEEE Trans. Comput., vol. 18, no. 1, pp. 99-102, Jan. 1993.
19. J. M. Muller, Elementary Functions: Algorithms and Implementations. Cambridge, MA: Birkhauser, 1997.
20. E. Antelo, T. Lang, and J. D. Bruguera, "Very-high radix circular CORDIC: Vectoring and unified rotation/vectoring," IEEE Trans. Comput., vol. 49, no. 7, pp. 727-739, Jul. 2000.
21. G. L. Haviland and A. A. Tuszynski, "A CORDIC arithmetic processor chip," IEEE Trans. Comput., vol. 29, pp. 68-79, 1980.
22. H. M. Ahmed, J. M. Delosme, and M. Morf, "Highly concurrent computing structures for matrix arithmetic and signal processing," IEEE Trans. Comput., vol. 15, no. 1, pp. 65-82, Jan. 1982.
23. J. M. Delosme, "A processor for two-dimensional symmetric eigenvalue and singular value arrays," in Proc. 21st Asilomar Conf. Circuits, Syst., Comput., 1987, pp. 217-221.
24. J. Ma, K. K. Parhi, and E. F. Deprettere, "Pipelined CORDIC-based cascade orthogonal IIR digital filters," IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 47, no. 11, pp. 1238-1253, Nov. 2000.
25. A. A. J. de Lange and Ed. F. Deprettere, "Design and implementation of a floating point quasi-systolic general purpose CORDIC rotator for high rate parallel data and signal processing," in Proc. IEEE Symp. Comput. Arithmetic, 1991, pp. 272-281.
26. E. Antelo, J. Villalba, D. Bruguera, and E. Zapata, "High performance rotation architectures based on the radix CORDIC algorithm," IEEE Trans. Comput., vol. 46, no. 8, pp. 855-870, Aug. 1997.
27. A. P. Chandrakasan, S. Sheng, and R. W. Brodersen, "Low power CMOS digital design," IEEE J. Solid-State Circuits, vol. 27, no. 4, pp. 473-484, Apr. 1992.
28. J. C. Chih and S. G. Chen, "Fast CORDIC algorithm based on a new recoding scheme for rotation angles and variable scale factors," J. VLSI Signal Process., vol. 33, pp. 19-29, Jan. 2003.
29. J. C. Kuo et al., "VLSI design of a variable-length FFT/IFFT processor for OFDM-based communication systems," EURASIP J. Appl. Signal Process., no. 13, pp. 1306-1316, Dec. 2003.
30. S. Y. Park and N. I. Cho, "Fixed-point error analysis of CORDIC processor based on the variance propagation formula," IEEE Trans. Circuits Syst. I, Fundam. Theory Appl., vol. 51, no. 3, pp. 573-584, Mar. 2004.