System architecture of an adaptive reconfigurable DSP computing engine

IEEE Transactions on Circuits and Systems for Video Technology

Volumn 8, Issue 1, 1998, Pages 54-73

  Wu, An Yeu ^a,c   Liu, K J Ray ^b,c   Raghupathy, Arun ^b  

^a NATIONAL CENTRAL UNIVERSITY   (Taiwan)

^b UNIVERSITY OF MARYLAND   (United States)

^c IEEE   (Taiwan)

Author keywords

Coordinate rotation digital computer (CORDIC); Discrete cosine transforms; FIR digital filters; IIR digital filters; Multirate processing; Quadrature mirror filter; Reconfigurable architectures

Indexed keywords

ADAPTIVE FILTERING; COMPUTER ARCHITECTURE; DIGITAL COMPUTERS; DIGITAL FILTERS; MATHEMATICAL TRANSFORMATIONS; PARALLEL PROCESSING SYSTEMS;

COORDINATE ROTATION DIGITAL COMPUTERS (COR DIC); DISCRETE COSINE TRANSFORMS; QUADRATURE MIRROR FILTERS;

DIGITAL SIGNAL PROCESSING;

EID: 0031996677     PISSN: 10518215     EISSN: None     Source Type: Journal    
DOI: 10.1109/76.660829     Document Type: Article

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