A 30Gb/s 1:4 demultiplexer in 0.12μm CMOS

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2003, Pages

  Rylyakov, Alexander ^a   Rylov, Sergey ^a   Ainspan, Herschel ^a   Gowda, Sudhir ^a  

^a IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BIT ERROR RATE; CMOS INTEGRATED CIRCUITS; DATA COMMUNICATION SYSTEMS; ELECTRIC CURRENTS; ELECTRIC POWER SUPPLIES TO APPARATUS; ERROR DETECTION; FLIP FLOP CIRCUITS; FREQUENCY DIVIDING CIRCUITS; INTEGRATED CIRCUIT LAYOUT; POLYSILICON; RESISTORS; SILICON ON INSULATOR TECHNOLOGY;

COMMON MODE REJECTION; DATA RATES; INTERNAL STATIC DIVIDER; POLYSILICON RESISTORS;

DEMULTIPLEXING;

EID: 0038306490     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (7)

1. H. Knapp, H.-D. Wohlmuth, M. Wurzer, M. Rest, "25GHz Static Frequency Divider and 25Gb/s Multiplexer in 0.12μm CMOS," ISSCC Digest of Technical Papers, pp. 302-303, 2002.
2. H. Wang, "A 1.8V 3mW 16.8GHz Frequency Divider in 0.25μm CMOS," ISSCC Digest of Technical Papers, pp. 196-197, 2000.
3. B.A. Floyd et al., "SOI and bulk CMOS frequency dividers operating above 15GHz," Electronic Letters, vol. 37, no. 10, pp. 617-618, 2001.
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5. J. Cao et al., "OC-192 Receiver in Standard 0.18μm CMOS," ISSCC Digest of Technical Papers, pp. 250-251, 2002.
6. L.K. Han et al., "A Modular 0.13μm Bulk CMOS Technology for High Performance and Low Power Applications," 2000 Symposium on VLSI Technology Digest of Technical Papers, pp. 12-13.
7. N. Zamder et al. "A 0.13μm SOI CMOS Technology for Lower-Power Digital and RF Applications," 2001 Symposium on VLSI Technology Digest of Technical Papers, pp. 85-86.