A 43Gb/s 2:1 selector IC in 90nm CMOS technology

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 47, Issue , 2004, Pages

  Yamamoto, Takuji ^a   Horinaka, Minoru ^a   Yamazaki, Daisuke ^a   Nomura, Hiroshi ^a   Hashimoto, Kouichi ^a   Onodera, Hiroyuki ^a  

^a FUJITSU LABORATORIES LTD   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

BIAS VOLTAGE; DRAIN BACKGATE CAPACITANCE; SUB CIRCUIT BLOCKS; TRANSCONDUCTOR;

BANDWIDTH; CAPACITANCE; DATA COMMUNICATION EQUIPMENT; ELECTRIC INDUCTORS; ELECTRIC POTENTIAL; ENERGY EFFICIENCY; SILICON;

CMOS INTEGRATED CIRCUITS;

EID: 2442651361     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)

1. D. Kehrer et al., "40Gb/s 2:1 Multiplexer and 1:2 Demultiplexer in 120nm CMOS," ISSCC Dig. Tech. Papers, pp. 344-345, 2003.
2. A. Rylyakov et al., "A 30Gb/s 1:4 Demultiplexer in 0.12μm CMOS," ISSCC Dig. Tech. Papers, pp. 176-177, 2003.
3. D. Shaeffer et al., "A 40/43Gb/s SONET OC-768 SiGe 4:1 MUX / CMU," ISSCC Dig. Tech. Papers, pp. 236-237, 2003.
4. Y. Nakasha et al., "A 43Gb/s Full-Rate-Clock 4:1 Multiplexer in InP-Based HEMT Technology," ISSCC Dig. Tech. Papers, pp. 190-191, 2002.