Modelling of the 1T-Bulk capacitor-less DRAM cell with improved performances: The way to scaling

Solid-State Electronics

Volumn 49, Issue 11 SPEC. ISS., 2005, Pages 1759-1766

  Ranica, R ^a   Villaret, A ^a   Malinge, P ^a   Candelier, P ^a   Masson, P ^b   Bouchakour, R ^b   Mazoyer, P ^a   Skotnicki, T ^a  

^a STMICROELECTRONICS   (France)

^b AIX MARSEILLE UNIVERSITÉ   (France)

Author keywords

DRAM; Embedded memories; Floating body effect; Scaled CMOS

Indexed keywords

CAPACITORS; CMOS INTEGRATED CIRCUITS; EMBEDDED SYSTEMS;

EMBEDDED MEMORIES; FLOATING-BODY EFFECTS; GATE LENGTH; SCALED CMOS;

DYNAMIC RANDOM ACCESS STORAGE;

EID: 28044467955     PISSN: 00381101     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.sse.2005.10.003     Document Type: Article

References (10)

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