A generic micro-architectural test plan approach for microprocessor verification

Proceedings - Design Automation Conference

Volumn , Issue , 2005, Pages 769-774

  Adir, Allon ^a   Azatchi, Hezi ^a   Bin, Eyal ^a   Peled, Ofer ^a   Shoikhet, Kirill ^a  

^a UNIVERSITY OF HAIFA   (Israel)

Author keywords

Coverage; Dynamic Verification; Generic Test Plan; Micro architecture; Test Generation

Indexed keywords

COMPUTER ARCHITECTURE; PLANNING; RISK ASSESSMENT; SYSTEMS ANALYSIS;

BUGS; MICRO-ARCHITECTURE; SYSTEMATIC PARTITIONING;

MICROPROCESSOR CHIPS;

EID: 27944504384     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/dac.2005.193919     Document Type: Conference Paper

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