On-line synthesis for partially reconfigurable FPGAs

Proceedings of the IEEE International Conference on VLSI Design

Volumn , Issue , 2005, Pages 663-668

  Huang, Renqiu ^a   Vemuri, Ranga ^a  

^a UNIVERSITY OF CINCINNATI   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ON-LINE SYNTHESIS; ON-LINE USAGE; SYNTHESIZERS; TASK ALLOCATION;

ALGORITHMS; INTEGRATED CIRCUIT LAYOUT; ROUTERS;

FIELD PROGRAMMABLE GATE ARRAYS;

EID: 27944473111     PISSN: 10639667     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICVD.2005.131     Document Type: Conference Paper

References (20)

1. S. N. Adya and I. L. Markov. Fixed-outline floorplanning through better local search. In IEEE Int. Conf. on Computer Design, pages 328-334, September 2001.
2. K. Bazargan, R. Kastner, and M. Sarrafzadeh. Fast Template Placement for Reconfigurable Computing Systems. IEEE Design and Test - Special Issue on Reconfigurable Computing, 17(1):68-83, Jan.-Mar. 2000.
3. K. Bazargan, S. Ogrenci, and M. Sarrafzadeh. Integrating scheduling and physical design into a coherent compilation cycle for reconfigurable computing architectures. In Proceedings of DAC, pages 635-640, Jun 2001.
4. G. Brebner. A Virtual Hardware Operating System for the Xilinx XC6200. In Proceedings of the 6th International Workshop on FPL, pages 327-336, 1996.
5. R. Camposano. Path-based scheduling for synthesis. IEEE Transactions on CAD, 10(1):85 - 93, 1991.
6. W. E. Dougherty and D. E. Thomas. Unifying behavioral synthesis and physical design. In Proceedings of the 37th conference on Design automation, pages 756 - 761, 2000.
7. N. Dutt and C. Ramachandran. Benchmarks for the 1992 high level synthesis workshop. Tech. Rep. 92-107, Dep. Inform. Comput. Sci., Univ. California, Irvin, 1992.
8. S. Guccione, D. Verkest, and I. Bolsens. Design technology for networked reconfigurable fpga platforms. In Proceedings of DATE, pages 994-997, Mar. 2002.
9. M. Handa and R. Vemuri. An efficient algorithm for finding empty space for online fpga placement. In Proceedings of DAC, pages 960-965, June 2004.
10. S. O. Memik, E. Bozorgzadeh, R. Kastner, and M. Sarrafzadeh. A super-scheduler for embedded reconfigurable systems. In Proceedings of ICCAD, pages 391 - 394, Nov 2001.
11. J. Nestor and D. Thomas. Behavioral synthesis with interfaces. In Proceedings of the IEEE Conference on Computer Aided Design, Nov 1986.
12. P. Paulin and J. Knight. Force directed scheduling for the behavioral synthesis of asics. IEEE Transactions on CAD, volume 8:661-679, Jun 1989.
13. G. J. Smit, P. J. Havinga, L. T. Smit, P. M. Heysters, and M. A. Rosien. Dynamic reconfiguration in mobile systems. In Proceedings of FPL, pages 171-181, sept. 2002.
14. H.-P. Su, A. C.-H. Wu, and Y. L. lin. A timing-driven soft-macro resynthesis method in interaction with chip floorplanning. In 36th DAC Proceedings, pages 262-267, 1999.
15. S. Tarafdar, M. Leeser, and Z. Yin. Integrating floorplanning in data-transfer based high-level synthesis. In Proceedings of ICCAD, pages 412-416, Nov. 1998.
16. H. Walder, C. Steiger, and M. Platzner. Fast Online Task Placement on FPGAs: Free Space Partitioning and 2D-Hashing. In Proceedings of IPDPS, April 2003.
17. G. Wigley and D. Kearney. The first real operating system for reconfigurable computers. In Proceedings of the 6th Australasian conference on Computer systems architecture, pages 130-137. IEEE Computer Society, 2001.
18. Xilinx Inc. virtex-II Pro Platform FPGA Handbook and ISE Manual.
19. M. Xu and F. J. Kurdahi. Layout-driven high level synthesis for fpga based architectures. Proceedings of the conference on DATE, pages 446-450, 1998.
20. J. Zhu and D. D. Gajski. Soft scheduling in high level synthesis. In Proceedings of the 36th ACM/IEEE conference on Design automation, pages 219 - 224, June 1999.