Integrating scheduling and physical design into a coherent compilation cycle for reconfigurable computing architectures

Proceedings - Design Automation Conference

Volumn , Issue , 2001, Pages 635-640

  Bazargan, Kia ^a   Ogrenci, Seda ^b   Sarrafzadeh, Majid ^b  

^a University of Minnesota   (United States)

^b Engineering IV   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; C (PROGRAMMING LANGUAGE); COMPUTATIONAL METHODS; COMPUTER ARCHITECTURE; FIELD PROGRAMMABLE GATE ARRAYS; PROGRAM COMPILERS; SCHEDULING;

COHERENT COMPILATION; RECONFIGURABLE COMPUTING SYSTEMS (RCS);

COMPUTER SYSTEMS;

EID: 0034848108     PISSN: 0738100X     EISSN: None     Source Type: Journal    
DOI: 10.1109/DAC.2001.156216     Document Type: Article

References (8)

1. Fast online placement for reconfigurable computing systems
2. Fast module mapping and placement for datapaths in FPGAs
3. Embedded tutorial: Reconfigurable computing: What, why, and implications for design automation
4. The roles of FPGAs in reprogrammable systems
5. A C to HDL compiler for pipeline processing on FPGAs
6. Compilation and pipeline synthesis for reconfigurable architectures
7. A C compiler for a processor with a reconfigurable functional unit