Partitioning-based approach to fast on-chip decap budgeting and minimization

Proceedings - Design Automation Conference

Volumn , Issue , 2005, Pages 170-175

  Li, Hang ^a   Qi, Zhenyu ^a   Tant, Sheldon X D ^a   Wu, Lifeng ^b   Cai, Yici ^c   Hong, Xianlong ^c  

^a University of California ^*  (United States)

^b CADENCE DESIGN SYSTEMS   (United States)

^c TSINGHUA UNIVERSITY   (China)

Author keywords

Decoupling Capacitor; IR drop; On Chip Power Grid Networks

Indexed keywords

ALGORITHMS; CAPACITANCE; CAPACITORS; COMPUTER WORKSTATIONS; INTEGRATED CIRCUIT LAYOUT; OPTIMIZATION; TIME DOMAIN ANALYSIS; VLSI CIRCUITS;

CONJUGATE GRADIENT (CG) APPROACH; DECOUPLING CAPACITORS; IR DROP; ON-CHIP POWER/GRID NETWORKS;

MICROPROCESSOR CHIPS;

EID: 27944470412     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1065579.1065627     Document Type: Conference Paper

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