Partitioning-based approach to fast on-chip decap budgeting and minimization

Proceedings - Design Automation Conference

Volumn , Issue , 2005, Pages 170-175

  Li, Hang ^a   Qi, Zhenyu ^a   Tant, Sheldon X D ^a   Wu, Lifeng ^b   Cai, Yici ^c   Hong, Xianlong ^c  

^a University of California Riverside   (United States)

^b CADENCE DESIGN SYSTEMS   (United States)

^c TSINGHUA UNIVERSITY   (China)

Author keywords

Decoupling Capacitor; IR drop; On Chip Power Grid Networks

Indexed keywords

ALGORITHMS; CAPACITANCE; CAPACITORS; COMPUTER WORKSTATIONS; INTEGRATED CIRCUIT LAYOUT; OPTIMIZATION; TIME DOMAIN ANALYSIS; VLSI CIRCUITS;

CONJUGATE GRADIENT (CG) APPROACH; DECOUPLING CAPACITORS; IR DROP; ON-CHIP POWER/GRID NETWORKS;

MICROPROCESSOR CHIPS;

EID: 27944470412     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1065579.1065627     Document Type: Conference Paper

References (12)

1. S. Bobba, T. Thorp, K. Aingaran, and D. Liu, "IC power distribution challeges," in Proc. Int. Conf. on Computer Aided Design (ICCAD), 2001, pp. 643-650.
2. H. H. Chen and D. D. Ling, "Power supply noise analysis methodology for deep-submicron VLSI chip design," in Proc. Design Automation Conf. (DAC), 1997, pp. 638-643.
3. E. Chiprout, "Fast flip-chip power grid analysis via locality and grid shells," in Proc. Int. Conf. on Computer Aided Design (ICCAD), Nov. 2004, pp. 485-488.
4. E. Chiprout and T. Nguyen, "Power analysis of large interconnect grids with multiple sources using model reduction," in Proc. European Conference on Circuit Theory and Design, Sept. 1999.
5. J. Fu, Z. Luo, X. Hong, Y. Cai, S. X.-D. Tan, and Z. Pan, "A fast decoupling capacitor budgeting algorithm for robust on-chip power delivery," in Proc. Asia South Pacific Design Automation Conf. (ASPDAC), Jan. 2004, pp. 505-510.
6. G. Karypis, R. Aggarwal, and V. K. S. Shekhar, "Multilevel hypergraph partitioning: application in VLSI domain," IEEE Trans. on Very Large Scale Integration (VLSI) Systems, vol. 7, no. 1, pp. 69-79, March 1999.
7. M. Pant, P. Pant, and D. Wills, "On-chip decoupling capacitor optimization using architectural level current signature prediction," in Proc. IEEE Midwest Symp. Circuits and Systems, 2000, pp. 772-775.
8. H. F. Qian, S. R. Nassif, and S. S. Sapatnekar, "Random walks in a supply network," in Proc. Design Automation Conf. (DAC), 2003, pp. 93-98.
9. C. K. S. Zhao, K. Roy, "Decoupling capacitance allocation and its application to power-supply noise-aware floorplanning," IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 21, no. 1, pp. 81-92, Jan. 2002.
10. L. Smith, "Decoupling capacitor calculations for cmos circuits," in Proc. IEEE Topical Meeting of Electrical Performance of Electronic Packaging, 1994, pp. 101-105.
11. H. Su, S. S. Sapatnekar, and S. R. Nassif, "Optimal decoupling capacitor sizing and placement for standard cell layout designs," IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 22, no. 4, April 2003.
12. J. Vlach and K. Singhal, Computer Methods for Circuit Analysis and Design. New York, NY: Van Nostrand Reinhold, 1995.