Static and dynamic on-chip test response evaluation using a two-mode comparator

Proceedings of the European Test Workshop

Volumn 2000-January, Issue , 2000, Pages 47-52

  De Venuto, D ^a   Ohletz, M J ^b   Matarrese, G ^a  

^a POLITECNICO DI BARI   (Italy)

^b LUCENT TECHNOLOGIES   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 85037581705     PISSN: 15301877     EISSN: 15581780     Source Type: Conference Proceeding    
DOI: 10.1109/ETW.2000.873778     Document Type: Conference Paper

References (8)

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2. R. D. Adams, E. S. Cooley, P. R. Hansen, A Self-Test Circuit for Evaluating Memory Sense-Amplifier Signals, pp. 217-225, 1997.
3. D. De Venuto, M. Ohletz, B. Riccb, On-Chip Checking of Analogue Circuits submitted for publication in IEE El. Lett. 2000.
4. D. De Venuto, M. J. Ohletz, "Bias-Programmable Hardware Reconfiguration for On-Chip Test Response Evaluation", Accepted for publication IMSTW, Motpellier, June 23-26, 2000.
5. H.H. Schreiber: " Fault Dictionary based upon Stimulus Design", Trans. Circuits and Systems, Vol. 26, No. 7, July 1979.
6. F. Corsi, D. De Venuto, C. Marzocca: "A time domain technique for analogue filter testing", Proc. of IEEE ETW, Cagliari, May 28-30, 1997.
7. D. De Venuto, F. Corsi, M.J. Ohletz: "Testing the analogue front-end of a mixed-signal pixel detector circuit using the complementarys ignal" Proc. of 4th 1EEE Inter. Mixed-Signal Testing Workshop, June 8-11, 1998.
8. M. J. Ohletz, Realistic Faults Mapping Scheme for the Fault Simulation of Integrated Analogue CMOS Circuits, Proc. ITC, pp.776-785, 1996.